Code: Alles auswählen
library ieee;
use ieee.std_logic_1164.all;
entity quine20240417 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240417 is
begin
y <= (not x3 and not x2 and x1) or
(x3 and x2 and not x1) or
(not x2 and x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240417testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240417testbench is
component quine20240417
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240417 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;
Code: Alles auswählen
0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 0
2 0 0 1 0 1
3 0 0 1 1 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
Gruppe 1:
2 0 0 1 0 1
Gruppe 2:
3 0 0 1 1 1
12 1 1 0 0 1
Gruppe 3:
11 1 0 1 1 1
13 1 1 0 1 1
2:3 0 0 1 -
3:11 - 0 1 1
12:13 1 1 0 -
Gruppe 1:
2:3 0 0 1 -
Gruppe 2:
12:13 1 1 0 -
Gruppe 2:
3:11 - 0 1 1
2:3 0 0 1 -
12:13 1 1 0 -
3:11 - 0 1 1
2 3 11 12 13
2:3 * *
12:13 * *
3:11 * *
2:3 0 0 1 -
12:13 1 1 0 -
3:11 - 0 1 1
y <= (not x3 and not x2 and x1) or
(x3 and x2 and not x1) or
(not x2 and x1 and x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240417 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240417 is
begin
y <= (not x3 and not x2 and x1) or
(x3 and x2 and not x1) or
(not x2 and x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240417testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240417testbench is
component quine20240417
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240417 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);