Re: Aufgaben und Übungen,

Ich lasse es mal so weit, ist noch nicht fertig

entity meinautomatenuebergangsnetz0001 is
port
(
	bin, ain, x: in bit;
	bout, aout: out bit
);
end;

entity meinautomatenausgangsschalnetz0001 is
port
(
	bin, ain, x: in bit;
	y: out bit
);
end;

entity rslatch0001 is
port
(
    r, s: in bit;
    q1, q2: inout bit
);
end;

entity dlatch0001 is
port
(
    d: in bit;
    q1, q2: out bit
);
end;

entity dmsflipflop0001 is
port
(
    d: in bit;
    clk: in bit;
    q: out bit
);
end;

architecture verhalten of meinautomatenuebergangsnetz0001 is
begin
	bout <= (not bin or ain or x);
	aout <= (x) or (bin and not ain);
end;

architecture verhalten of meinautomatenausgangsschalnetz0001 is
begin
	y <= (not ain and not x) or (not bin and ain and x);
end;

architecture verhalten of rslatch0001 is
begin
    q1 <= (r nor q2);
    q2 <= (s nor q1);
end;

architecture verhalten of dlatch0001 is
component rslatch0001
port
(
    r, s: in bit;
    q1, q2: out bit
);
end component;
signal nd: bit;
begin
    nd <= not d;
    l: rslatch0001 port map (d, nd, q1, q2);
end;

architecture verhalten of dmsflipflop0001 is
component dlatch0001
port
(
    d: in bit;
    q1, q2: out bit;
);
signal invertedclk
begin

end;