0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 0
0 0 0 0 0 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
6 0 1 1 0 1
7 0 1 1 1 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
2 0 0 1 0 1
4 0 1 0 0 1
Gruppe 2:
3 0 0 1 1 1
6 0 1 1 0 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
0:2 0 0 - 0
0:4 0 - 0 0
2:3 0 0 1 -
2:6 0 - 1 0
2:10 - 0 1 0
4:6 0 1 - 0
4:12 - 1 0 0
3:7 0 - 1 1
3:11 - 0 1 1
6:7 0 1 1 -
6:14 - 1 1 0
9:11 1 0 - 1
10:11 1 0 1 -
9:13 1 - 0 1
10:14 1 - 1 0
12:13 1 1 0 -
12:14 1 1 - 0
0:2 0 0 - 0
0:4 0 - 0 0
2:3 0 0 1 -
2:6 0 - 1 0
4:6 0 1 - 0
3:11 - 0 1 1
6:14 - 1 1 0
4:12 - 1 0 0
2:10 - 0 1 0
9:13 1 - 0 1
10:14 1 - 1 0
3:7 0 - 1 1
9:11 1 0 - 1
12:14 1 1 - 0
10:11 1 0 1 -
6:7 0 1 1 -
12:13 1 1 0 -
Gruppe 2:
3:11 - 0 1 1
6:14 - 1 1 0
Gruppe 1:
4:12 - 1 0 0
2:10 - 0 1 0
Gruppe 2:
9:13 1 - 0 1
10:14 1 - 1 0
3:7 0 - 1 1
Gruppe 2:
9:11 1 0 - 1
12:14 1 1 - 0
Gruppe 2:
10:11 1 0 1 -
6:7 0 1 1 -
12:13 1 1 0 -
Gruppe 2:
3:11 - 0 1 1
6:14 - 1 1 0
Gruppe 1:
4:12 - 1 0 0
2:10 - 0 1 0
3:11:2:10 - - 1 0
6:14:4:12 - 1 - 0
Gruppe 2:
9:13 1 - 0 1
10:14 1 - 1 0
3:7 0 - 1 1
Gruppe 2:
9:11 1 0 - 1
12:14 1 1 - 0
Gruppe 2:
10:11 1 0 1 -
6:7 0 1 1 -
12:13 1 1 0 -
3:11:2:10 - - 1 0
6:14:4:12 - 1 - 0
9:13 1 - 0 1
10:14 1 - 1 0
3:7 0 - 1 1
9:11 1 0 - 1
12:14 1 1 - 0
10:11 1 0 1 -
6:7 0 1 1 -
12:13 1 1 0 -
2 3 4 6 7 9 10 11 12 13 14
3:11:2:10 * * * *
6:14:4:12 * * * *
9:13 * *
10:14 * *
3:7 * *
9:11 * *
12:14 * *
10:11 * *
6:7 * *
12:13 * *
2 3 4 6 7 9 10 11 12 13 14
3:11:2:10 * * * *
6:14:4:12 * * * *
9:13 * *
10:14 * *
3:7 * *
3:11:2:10 - - 1 0
6:14:4:12 - 1 - 0
9:13 1 - 0 1
10:14 1 - 1 0
3:7 0 - 1 1
y <= (x1 and not x0) or
(x2 and not x0) or
(x3 and not x1 and x0) or
(x3 and x1 and not x0) or
(not x3 and x1 and x0)
entity meinschaltnetz is
port
(
x3, x2, x1, x0: in bit;
y: out bit
);
end;
architecture verhalten of meinschaltnetz is
begin
y <= (x1 and not x0) or
(x2 and not x0) or
(x3 and not x1 and x0) or
(x3 and x1 and not x0) or
(not x3 and x1 and x0)
end;