Re: VHDL

-- ich habe jetzt erst mal das:

use std.textio.all;

entity myhello is
port
(
    a0, a1, a2, a3: inout bit;
    b0, b1, b2, b3: in bit;
    s:              in bit;
    y0, y1, y2, y3: out bit
);
end;


architecture behaviour of myhello is
begin
    process
        variable l : line;
    begin
        if (a0='0') then
            a0 <= '1';
            write (l, String'("Hello world!"));
            writeline (output, l);
        else
            a0 <= '0';
            write (l, String'("das ist ein Standardspruch"));
            writeline (output, l);
        end if;
        wait;
    end process;
end behaviour;