Re: MIPS auf Xilinx FPGA

-- So

entity my_rs_latch is
port
(
    r, s: in bit;
    q1, q2: inout bit
);
end;

entity clock_state_controlled_rs_latch is
port (
    s, r: in bit;
    c: in bit;
    q1, q2: inout bit
);
end;

architecture Behavioral of my_rs_latch is
begin
    q1 <= (not r) nor q2;
    q2 <= (not s) nor q1;
end Behavioral;

architecture Behavioral of clock_state_controlled_rs_latch is
    component my_rs_latch
    port
    (
        r, s: in bit;
        q1, q2: inout bit
    );
    end component;
    signal s1, r1: bit;
begin
    r1 <= r and c;
    s1 <= s and c;
    rs: my_rs_latch port map (r=>r1, s=>s1, q1=>q1, q2=>q2);
end Behavioral;