Re: MIPS auf Xilinx FPGA

entity my_rs_latch is
port
(
    r, s: in bit;
    q1, q2: inout bit
);
end;

entity clock_state_controlled_rs_latch is
port (
    s, r: in bit;
    c: in bit;
    q1, q2: inout bit
);
end;

entity clock_state_controlled_d_latch is
port (
    d: in bit;
    c: in bit;
    q1, q2: out bit
);
end;

entity ms_d_flip_flop is
port (
    d: in bit;
    q: out bit;
    c: in bit
);
end;

entity reg is
port
(
    d1, d2, d3, d4: in bit;
    q1, q2, q3, q4: out bit;
    c: in bit
);
end;

architecture Behavioral of my_rs_latch is
begin
    q1 <= (not r) nor q2;
    q2 <= (not s) nor q1;
end Behavioral;

architecture Behavioral of clock_state_controlled_rs_latch is
    component my_rs_latch
    port
    (
        r, s: in bit;
        q1, q2: out bit
    );
    end component;
    signal s1, r1: bit;
begin
    r1 <= r and c;
    s1 <= s and c;
    rs: my_rs_latch port map (r=>r1, s=>s1, q1=>q1, q2=>q2);
end Behavioral;

architecture Behavioral of clock_state_controlled_d_latch is
    component clock_state_controlled_rs_latch
    port
    (
        r: in bit;
        s: in bit;
        q1, q2: out bit
    );
    end component;
    signal notd: bit;
begin
    notd <= d;
    rs: clock_state_controlled_rs_latch port map (r=>d, s=>notd, q1=>q1, q2=>q2);
end Behavioral;

architecture Behavioral of ms_d_flip_flop is
    component clock_state_controlled_d_latch
    port
    (
        d: in bit;
        q1, q2: out bit;
        c: in bit
    );
    end component;
    signal notc, d1: bit;
begin
    dlatch1: clock_state_controlled_d_latch port map (d=>d, q1=>d1, c=>c);
    notc <= not c;
    dlatch2: clock_state_controlled_d_latch port map (d=>d1, q1=>q, c=>c);
end Behavioral;

architecture Behavioral of reg is
    component ms_d_flip_flop is
    port
    (
        d: in bit;
        q: out bit;
        c: in bit
    );
    end component;
begin
    bit1: ms_d_flip_flop port map (d=>d1, q=>q1, c=>c);
    bit2: ms_d_flip_flop port map (d=>d2, q=>q2, c=>c);
    bit3: ms_d_flip_flop port map (d=>d3, q=>q3, c=>c);
    bit4: ms_d_flip_flop port map (d=>d4, q=>q4, c=>c);
end;