Re: Aufgaben und Übungen,

-- so das gerade war unvollst"andig

entity meinautomat0028ausgangschaltnetz is
port
(
 a, b, x: in bit;
 y0, y1, y2: out bit
);
end;

entity meinautomat0028uebergangsschaltnetz is
port
(
 a, b: inout bit;
 x: in bit
);
end;

architecture verhalten of meinautomat0028ausgangschaltnetz is
begin
 y0 <= (not b and x) or
 (b and a);
 y1 <= (b and not a and not x);
 y2 <= (b and a and x);
end;

architecture verhalten of meinautomat0028uebergangsschaltnetz is
begin
 b <= (b and not a) or
 (b and x);
 a <= (not b and x) or
 (not a and not x) or
 (b and a and x);
end;

entity meinautomat0028rslatch is
port (
    q1, q2: inout bit;
    r, s: in bit
);
end;

architecture verhalten of meinautomat0028rslatch is
begin
    q1 <= ((not r) nor q2);
    q2 <= ((not s) nor q1);
end;

entity meinautomat0028rslatchtaktgesteuert is
port (
    q1, q2: inout bit;
    r, s, c: in bit
);
end;

architecture verhalten of meinautomat0028rslatchtaktgesteuert is
    component meinautomat0028rslatch
    port (
        q1, q2: inout bit;
        r, s: in bit
    );
    end component;
    signal r1, s1: bit;
begin
    instanzrslatch: meinautomat0028rslatch PORT MAP (r=>r1, s=>s1, q1=>q1, q2=>q2);
    r1 <= c and r;
    s1 <= c and s;
end;

entity meinautomat0028dlatch is
port
(
    q1, q2: inout bit;
    d, c: in bit
);
end;

architecture verhalten of meinautomat0028dlatch is
    component meinautomat0028rslatchtaktgesteuert
    port
    (
        q1, q2: inout bit;
        r, s, c: in bit
    );
    end component;
    signal r1, s1: bit;
begin
    instanzrslatchtaktgesteuert: meinautomat0028rslatchtaktgesteuert PORT MAP (r=>r1, s=>s1, q1=>q1, q2=>q2, c=>c);
    r1 <= d;
    s1 <= not d;
end;