Re: Aufgaben und Übungen,

b a x b a y
0 0 0 0 1 1 0
1 0 0 1 0 1 0
2 0 1 0 1 1 0
3 0 1 1 1 0 0
4 1 0 0 1 1 1
5 1 0 1 0 1 0
6 1 1 0 1 0 0
7 1 1 1 0 1 0

 b a x b
0 0 0 0 1
1 0 0 1 0
2 0 1 0 1
3 0 1 1 1
4 1 0 0 1
5 1 0 1 0
6 1 1 0 1
7 1 1 1 0

 b a x a
0 0 0 0 1
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
5 1 0 1 1
6 1 1 0 0
7 1 1 1 1

 b a x y
0 0 0 0 0
1 0 0 1 0
2 0 1 0 0
3 0 1 1 0
4 1 0 0 1
5 1 0 1 0
6 1 1 0 0
7 1 1 1 0

 b a x b
0 0 0 0 1
2 0 1 0 1
3 0 1 1 1
4 1 0 0 1
6 1 1 0 1

 b a x a
0 0 0 0 1
1 0 0 1 1
2 0 1 0 1
4 1 0 0 1
5 1 0 1 1
7 1 1 1 1

 b a x y
4 1 0 0 1

 b a x b
Gruppe 0:
0 0 0 0 1
Gruppe 1:
2 0 1 0 1
4 1 0 0 1
Gruppe 2:
3 0 1 1 1
6 1 1 0 1

 b a x a
Gruppe 0:
0 0 0 0 1
Gruppe 1:
1 0 0 1 1
2 0 1 0 1
4 1 0 0 1
Gruppe 2:
5 1 0 1 1
Gruppe 3:
7 1 1 1 1

 b a x y
Gruppe 1:
4 1 0 0 1

 b a x b
Gruppe 0:
0 0 0 0 1
Gruppe 1:
2 0 1 0 1
4 1 0 0 1
Gruppe 2:
3 0 1 1 1
6 1 1 0 1

0:2 0 - 0
0:4 - 0 0
2:3 0 1 -
2:6 - 1 0
4:6 1 - 0

0:2 0 - 0
4:6 1 - 0
2:6 - 1 0
0:4 - 0 0
2:3 0 1 -

0:2:4:6 - - 0
2:6:0:4 - - 0
2:3 0 1 -

 0 2 3 4 6
2:6:0:4 * * * *
2:3 * *

b <= (not x) or
 (not b and a);
b <= not (x and
 (b or not a))

 b a x a
Gruppe 0:
0 0 0 0 1
Gruppe 1:
1 0 0 1 1
2 0 1 0 1
4 1 0 0 1
Gruppe 2:
5 1 0 1 1
Gruppe 3:
7 1 1 1 1

0:1 0 0 -
0:2 0 - 0
0:4 - 0 0
1:5 - 0 1
4:5 1 0 -
5:7 1 - 1

0:4 - 0 0
1:5 - 0 1
4:5 1 0 -
0:1 0 0 -
5:7 1 - 1
0:2 0 - 0

0:4:1:5 - 0 -
4:5:0:1 - 0 -
5:7 1 - 1
0:2 0 - 0

 0 1 2 4 5 7
4:5:0:1 * * * *
5:7 * *
0:2 * *

a <= (not a) or
 (b and x) or
 (not b and not x);
a <= not(a and
 (not b or not x) and
 (b or x)
 );

 b a x y
Gruppe 1:
4 1 0 0 1

y <= (b and not a and not x);
y <= not (not b or a or x);

b <= (not x) or
 (not b and a);
b <= not (x and
 (b or not a))
a <= (not a) or
 (b and x) or
 (not b and not x);
a <= not(a and
 (not b or not x) and
 (b or x)
 );
y <= (b and not a and not x);
y <= not (not b or a or x);

library ieee;
use ieee.std_logic_1164.all;

entity ausgangsschaltnetz0042 is
port
(
 a, b, x: in std_logic;
 y: out std_logic
);
end;

architecture verhalten of ausgangsschaltnetz0042 is
begin
 y <= (b and not a and not x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity uebergangsschaltnetz0042 is
port
(
 a, b, x: in std_logic;
 aout, bout: out std_logic
);
end;

architecture verhalten of uebergangsschaltnetz0042 is
begin
 bout <= (not x) or
 (not b and a);
 aout <= (not a) or
 (b and x) or
 (not b and not x);
end;