Nächste Seite: Re: Aufgaben und Übungen, Aufwärts: Graphen, Schaltwerke und Zahlen Vorherige Seite: Re: Aufgaben und Übungen,
./generatetestbench >> quine0050.txt
Ich habe dies Mal ausversehen geschrieben
./generatetestbench > quine0050.txt
Dann war das schöne Schaltnetz weg, ich musste noch mal
In Zukunft nehme ich lieber
cat quine0050.txt \$(./generatetestbench) > quine0050b.txt
Egal. Hier das Ergebnis
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 0
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
14 1 1 1 0 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
8 1 0 0 0 1
Gruppe 2:
9 1 0 0 1 1
Gruppe 3:
7 0 1 1 1 1
14 1 1 1 0 1
0:1 0 0 0 -
0:2 0 0 - 0
0:8 - 0 0 0
1:9 - 0 0 1
8:9 1 0 0 -
7 0 1 1 1
14 1 1 1 0
Gruppe 0:
0:1 0 0 0 -
Gruppe 1:
8:9 1 0 0 -
Gruppe 0:
0:2 0 0 - 0
Gruppe 0:
0:8 - 0 0 0
Gruppe 1:
1:9 - 0 0 1
7 0 1 1 1
14 1 1 1 0
Gruppe 0:
0:1 0 0 0 -
Gruppe 1:
8:9 1 0 0 -
0:1:8:9 - 0 0 -
Gruppe 0:
0:2 0 0 - 0
Gruppe 0:
0:8 - 0 0 0
Gruppe 1:
1:9 - 0 0 1
0:8:1:9 - 0 0 -
7 0 1 1 1
14 1 1 1 0
0:1:8:9 - 0 0 -
0:2 0 0 - 0
7 0 1 1 1
14 1 1 1 0
0 1 2 7 8 9 14
0:1:8:9 * * * *
0:2 * *
7 *
14 *
y <= (not x2 and not x1) or
(not x3 and not x2 and not x0) or
(not x3 and x2 and x1 and x0) or
(x3 and x2 and x1 and not x0);
y <= not (
(x2 or x1) and
(x3 or x2 or x0) and
(x3 or not x2 or not x1 or not x0) and
(not x3 or not x2 or not x1 or x0)
);
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
entity meinschaltnetz0050 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0050 is
begin
y <= (not x2 and not x1) or
(not x3 and not x2 and not x0) or
(not x3 and x2 and x1 and x0) or
(x3 and x2 and x1 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
entity meinetestbench0050 is
port (
y: out std_logic
);
end;
architecture verhalten of meinetestbench0050 is
component meinschaltnetz0050
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
sn: meinschaltnetz0050 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;
0 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 0 4 0 1 0 0 0 5 0 1 0 1 0 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 0 11 1 0 1 1 0 12 1 1 0 0 0 13 1 1 0 1 0 14 1 1 1 0 1 15 1 1 1 1 0
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
entity meinschaltnetz0050 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0050 is
begin
y <= (not x2 and not x1) or
(not x3 and not x2 and not x0) or
(not x3 and x2 and x1 and x0) or
(x3 and x2 and x1 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
entity meinetestbench0050 is
port (
y: out std_logic
);
end;
architecture verhalten of meinetestbench0050 is
component meinschaltnetz0050
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
sn: meinschaltnetz0050 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;
cut:
tail -n 52 quine0050.txt > quine0050.vhdl
compile:
ghdl -a quine0050.vhdl
sim:
ghdl -r meinetestbench0050 --wave=wave0050.ghw
gtkwave wave0050.ghw
[/img]</CODE>}
\section{ Re: Aufgaben und "Ubungen, }
\begin{verbatim}
b a x b a y
0 0 0 0 0 0 0
1 0 0 1 1 0 1
2 0 1 0 0 0 1
3 0 1 1 1 1 0
4 1 0 0 1 0 0
5 1 0 1 0 1 1
6 1 1 0 0 0 1
7 1 1 1 0 1 1
b a x b
0 0 0 0 0
1 0 0 1 1
2 0 1 0 0
3 0 1 1 1
4 1 0 0 1
5 1 0 1 0
6 1 1 0 0
7 1 1 1 0
b a x a
0 0 0 0 0
1 0 0 1 0
2 0 1 0 0
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1
6 1 1 0 0
7 1 1 1 1
b a x y
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 0
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1
b a x b
1 0 0 1 1
3 0 1 1 1
4 1 0 0 1
b a x a
3 0 1 1 1
5 1 0 1 1
7 1 1 1 1
b a x y
1 0 0 1 1
2 0 1 0 1
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1
b a x b
Gruppe 1:
1 0 0 1 1
4 1 0 0 1
Gruppe 2:
3 0 1 1 1
b a x a
Gruppe 2:
3 0 1 1 1
5 1 0 1 1
Gruppe 3:
7 1 1 1 1
b a x y
Gruppe 1:
1 0 0 1 1
2 0 1 0 1
Gruppe 2:
5 1 0 1 1
6 1 1 0 1
Gruppe 3:
7 1 1 1 1
b a x b
Gruppe 1:
1 0 0 1 1
4 1 0 0 1
Gruppe 2:
3 0 1 1 1
1:3 0 - 1
4 1 0 0
bout <= (not b and x) or
(b and not a and not x);
bout <= not (
(b or not x) and
(not b or a or x)
);
b a x a
Gruppe 2:
3 0 1 1 1
5 1 0 1 1
Gruppe 3:
7 1 1 1 1
3:7 - 1 1
5:7 1 - 1
aout <= (a and x) or
(b and x);
aout <= not (
(not a or not x) and
(not b or not x)
);
b a x y
Gruppe 1:
1 0 0 1 1
2 0 1 0 1
Gruppe 2:
5 1 0 1 1
6 1 1 0 1
Gruppe 3:
7 1 1 1 1
1:5 - 0 1
2:6 - 1 0
5:7 1 - 1
6:7 1 1 -
1 2 5 6 7
1:5 * *
2:6 * *
5:7 * *
6:7 * *
1 2 5 6 7
1:5 * *
2:6 * *
6:7 * *
1:5 - 0 1
2:6 - 1 0
6:7 1 1 -
y <= (not a and x) or
(a and not x) or
(b and a);
y <= not (
(a or not x) and
(not a or x) and
(not b or not a)
);
bout <= (not b and x) or
(b and not a and not x);
aout <= (a and x) or
(b and x);
y <= (not a and x) or
(a and not x) or
(b and a);
library ieee;
use ieee.std_logic_1164.all;
entity meinuebergangsschaltnetz0050 is
port (
b, a, x: in std_logic;
bout, aout: out std_logic
);
end;
architecture verhalten of meinuebergangsschaltnetz0050 is
begin
bout <= (not b and x) or
(b and not a and not x);
aout <= (a and x) or
(b and x);
end;
library ieee;
use ieee.std_logic_1164.all;
entity meinausgangsschaltnetz0050 is
port (
a, b, x: in std_logic;
y: out std_logic
);
end;
architecture verhalten of meinausgangsschaltnetz0050 is
begin
y <= (not a and x) or
(a and not x) or
(b and a);
end;
library ieee;
use ieee.std_logic_1164.all;
entity meinetestbench0050automat is
port (
y: out std_logic;
bout, aout: out std_logic
);
end;
architecture verhalten of meinetestbench0050automat is
component meinuebergangsschaltnetz0050
port (
b, a, x: in std_logic;
bout, aout: out std_logic
);
end component;
component meinausgangsschaltnetz0050
port(
b, a, x: in std_logic;
y: out std_logic
);
end component;
signal b, a, x: std_logic;
begin
sn1: meinausgangsschaltnetz0050 PORT MAP (b=>b, a=>a, x=>x, y=>y);
sn2: meinuebergangsschaltnetz0050 PORT MAP (b=>b, a=>a, x=>x, bout=>bout, aout=>aout);
b a x b a y 0 0 0 0 0 0 0 1 0 0 1 1 0 1 2 0 1 0 0 0 1 3 0 1 1 1 1 0 4 1 0 0 1 0 0 5 1 0 1 0 1 1 6 1 1 0 0 0 1 7 1 1 1 0 1 1
library ieee; use ieee.std_logic_1164.all; entity meinuebergangsschaltnetz0050 is port ( b, a, x: in std_logic; bout, aout: out std_logic ); end; architecture verhalten of meinuebergangsschaltnetz0050 is begin bout <= (not b and x) or (b and not a and not x); aout <= (a and x) or (b and x); end; library ieee; use ieee.std_logic_1164.all; entity meinausgangsschaltnetz0050 is port ( a, b, x: in std_logic; y: out std_logic ); end; architecture verhalten of meinausgangsschaltnetz0050 is begin y <= (not a and x) or (a and not x) or (b and a); end; library ieee; use ieee.std_logic_1164.all; entity meinetestbench0050automat is port ( y: out std_logic; bout, aout: out std_logic ); end; architecture verhalten of meinetestbench0050automat is component meinuebergangsschaltnetz0050 port ( b, a, x: in std_logic; bout, aout: out std_logic ); end component; component meinausgangsschaltnetz0050 port( b, a, x: in std_logic; y: out std_logic ); end component; signal b, a, x: std_logic; begin sn1: meinausgangsschaltnetz0050 PORT MAP (b=>b, a=>a, x=>x, y=>y); sn2: meinuebergangsschaltnetz0050 PORT MAP (b=>b, a=>a, x=>x, bout=>bout, aout=>aout); x <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns; a <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns; b <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns; end;
testbench: gcc generatetestbench4.c -o generatetestbench4 ./generatetestbench4 > textbench.tmp cat automat0050.txt textbench.tmp > automat0050b.txt echo "end;" >> automat0050b.txt tail: tail -n 80 automat0050b.txt > automat0050.vhdl compile: ghdl -a automat0050.vhdl sim: ghdl -r meinetestbench0050automat --wave=wave0050automat.ghw gtkwave wave0050automat.ghw
