Nächste Seite: Re: Aufgaben und Übungen, Aufwärts: Graphen, Schaltwerke und Zahlen Vorherige Seite: Re: Neuer Automaten Generator
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
0 0 0 0 0 1
1 0 0 0 1 1
3 0 0 1 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
1 0 0 0 1 1
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
6 0 1 1 0 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
0:1 0 0 0 -
0:8 - 0 0 0
1:3 0 0 - 1
1:12 1 - 0 0
3:7 0 - 1 1
12:13 1 1 - 0
6:14 - 1 1 0
7:15 - 1 1 1
13:15 1 1 - 1
14:15 1 1 1 -
0:1 0 0 0 -
14:15 1 1 1 -
1:12 1 - 0 0
3:7 0 - 1 1
12:13 1 1 - 0
13:15 1 1 - 1
1:3 0 0 - 1
6:14 - 1 1 0
7:15 - 1 1 1
0:8 - 0 0 0
Gruppe 0:
0:1 0 0 0 -
Gruppe 1:
14:15 1 1 1 -
Gruppe 1:
1:12 1 - 0 0
Gruppe 2:
3:7 0 - 1 1
Gruppe 1:
1:3 0 0 - 1
Gruppe 2:
12:13 1 1 - 0
Gruppe 3:
13:15 1 1 - 1
Gruppe 0:
0:8 - 0 0 0
Gruppe 2:
6:14 - 1 1 0
Gruppe 3:
7:15 - 1 1 1
0:1 0 0 0 -
14:15 1 1 1 -
1:12 1 - 0 0
3:7 0 - 1 1
Gruppe 1:
1:3 0 0 - 1
Gruppe 2:
12:13 1 1 - 0
Gruppe 3:
13:15 1 1 - 1
12:13:13:15 1 1 - -
Gruppe 0:
0:8 - 0 0 0
Gruppe 2:
6:14 - 1 1 0
Gruppe 3:
7:15 - 1 1 1
6:14:7:15 - 1 1 -
0:1 0 0 0 -
14:15 1 1 1 -
1:12 1 - 0 0
3:7 0 - 1 1
1:3 0 0 - 1
12:13:13:15 1 1 - -
0:8 - 0 0 0
6:14:7:15 - 1 1 -
0 1 3 6 7 8 12 13 14 15
0:1 * *
14:15 * *
1:12 * *
3:7 * *
1:3 * *
12:13:13:15 * * *
0:8 * *
6:14:7:15 * * * +
0 1 3 6 7 8 12 13 14 15
1:12 * *
3:7 * *
12:13:13:15 * * *
0:8 * *
6:14:7:15 * * * *
1:12 1 - 0 0
3:7 0 - 1 1
12:13:13:15 1 1 - -
0:8 - 0 0 0
6:14:7:15 - 1 1 -
y <= (x3 and not x1 and not x0) or
(not x3 and x1 and x0) or
(x3 and x2) or
(not x2 and not x1 and not x0) or
(x2 and x1);
y <= not ((not x3 or x1 or x0) and
(x3 or not x1 or not x0) and
(not x3 or not x2) and
(x2 or x1 or x0) and
(not x2 or not x1));
library ieee;
use ieee.std_logic_1164.all;
entity quine20240131 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240131 is
begin
y <= (x3 and not x1 and not x0) or
(not x3 and x1 and x0) or
(x3 and x2) or
(not x2 and not x1 and not x0) or
(x2 and x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240131testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240131testbench is
component quine20240131
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240131 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240131 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240131 is
begin
y <= (x3 and not x1 and not x0) or
(not x3 and x1 and x0) or
(x3 and x2) or
(not x2 and not x1 and not x0) or
(x2 and x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240131testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240131testbench is
component quine20240131
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240131 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;
Da ist noch ein Fehler drin, am Anfang.
1:12 ist falsch
Das muss heissen, 8:12 und deswegen wurde die Primimplikanten Tafel falsch.
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
0 0 0 0 0 1
1 0 0 0 1 1
3 0 0 1 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
1 0 0 0 1 1
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
6 0 1 1 0 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
0:1 0 0 0 -
0:8 - 0 0 0
1:3 0 0 - 1
8:12 1 - 0 0
3:7 0 - 1 1
12:13 1 1 - 0
6:14 - 1 1 0
7:15 - 1 1 1
13:15 1 1 - 1
14:15 1 1 1 -
0:1 0 0 0 -
14:15 1 1 1 -
8:12 1 - 0 0
3:7 0 - 1 1
12:13 1 1 - 0
13:15 1 1 - 1
1:3 0 0 - 1
6:14 - 1 1 0
7:15 - 1 1 1
0:8 - 0 0 0
Gruppe 0:
0:1 0 0 0 -
Gruppe 1:
14:15 1 1 1 -
Gruppe 1:
8:12 1 - 0 0
Gruppe 2:
3:7 0 - 1 1
Gruppe 1:
1:3 0 0 - 1
Gruppe 2:
12:13 1 1 - 0
Gruppe 3:
13:15 1 1 - 1
Gruppe 0:
0:8 - 0 0 0
Gruppe 2:
6:14 - 1 1 0
Gruppe 3:
7:15 - 1 1 1
0:1 0 0 0 -
14:15 1 1 1 -
8:12 1 - 0 0
3:7 0 - 1 1
Gruppe 1:
1:3 0 0 - 1
Gruppe 2:
12:13 1 1 - 0
Gruppe 3:
13:15 1 1 - 1
12:13:13:15 1 1 - -
Gruppe 0:
0:8 - 0 0 0
Gruppe 2:
6:14 - 1 1 0
Gruppe 3:
7:15 - 1 1 1
6:14:7:15 - 1 1 -
0:1 0 0 0 -
14:15 1 1 1 -
8:12 1 - 0 0
3:7 0 - 1 1
1:3 0 0 - 1
12:13:13:15 1 1 - -
0:8 - 0 0 0
6:14:7:15 - 1 1 -
0 1 3 6 7 8 12 13 14 15
0:1 * *
14:15 * *
8:12 * *
3:7 * *
1:3 * *
12:13:13:15 * * *
0:8 * *
6:14:7:15 * * * *
0 1 3 6 7 8 12 13 14 15
1:3 * *
12:13:13:15 * * *
0:8 * *
6:14:7:15 * * * *
1:3 0 0 - 1
12:13:13:15 1 1 - -
0:8 - 0 0 0
6:14:7:15 - 1 1 -
y <= (not x3 and not x2 and x0) or
(x3 and x2) or
(not x2 and not x1 and not x0) or
(x2 and x1);
y <= not ((x3 or x2 or not x0) and
(not x3 or not x2) and
(x2 or x1 or x0) and
(not x2 or not x1)
);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240131 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240131 is
begin
y <= (not x3 and not x2 and x0) or
(x3 and x2) or
(not x2 and not x1 and not x0) or
(x2 and x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240131testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240131testbench is
component quine20240131
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240131 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240131 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240131 is
begin
y <= (not x3 and not x2 and x0) or
(x3 and x2) or
(not x2 and not x1 and not x0) or
(x2 and x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240131testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240131testbench is
component quine20240131
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240131 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;