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Da ist irgendwo ein fluechtigkeitsfehler drin aber ich muss jetzt aufhoeren. Mache Pause.
1.) Rechne die Zahl in binaer Darstellung in eine Dezimale Darstellung um
0010011010110110b 9910d
2.) Rechne die Zahl in dezimal darstellung in eine Binaerdarstellung um
54282 1101010000001010
3.) Addiere die drei Zahlen schriftlich
7644
+ 4647
+ 6536
-----------------
18827
4.) Subtrahiere die letzten drei Zahlen schriftlich von der ersten schriftlich
23718
- 14922
- 11076
- 6409
-----------------
-8689
5.) Rechne die Zahl ins zweier komplement um, mit 8 Bit - und subtrahiere diese zahl von der ersten und rechne das Ergebnis nach dezimal
-75 -47 = -122
10110101 11010001 = 10000110
6.) Multipliziere die zwei Zahlen schriftlich
651016794*60756 = 822507400
7.) Dividiere die zwei Zahlen schriftlich
1508975826/55078 = 27397
8.) Errechne x Logarithmisch mit dem Taschenrechner
62728\^x = 1847342551
Rechne die Zahl in IEEE-754 um 25277.992188
Irgendein Fehler drin geht gerade nicht.
0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 0
0 0 0 0 0 1
2 0 0 1 0 1
4 0 1 0 0 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
12 1 1 0 0 1
14 1 1 1 0 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
6 0 1 1 0 1
9 1 0 0 1 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
14 1 1 1 0 1
0:2 0 0 - 0
0:4 0 - 0 0
0:8 - 0 0 0
2:6 0 - 1 0
4:6 0 1 - 0
4:12 - 1 0 0
8:9 1 0 0 -
8:12 1 - 0 0
6:7 0 1 1 -
6:14 - 1 1 0
12:14 1 1 - 0
8:9 1 0 0 -
6:7 0 1 1 -
0:2 0 0 - 0
4:6 0 1 - 0
12:14 1 1 - 0
0:4 0 - 0 0
2:6 0 - 1 0
8:12 1 - 0 0
0:8 - 0 0 0
4:12 - 1 0 0
6:14 - 1 1 0
8:9 1 0 0 -
6:7 0 1 1 -
0:2 0 0 - 0
4:6 0 1 - 0
12:14 1 1 - 0
0:2:4:6 0 - - 0
4:6:12:14 - 1 - 0
0:4 0 - 0 0
2:6 0 - 1 0
8:12 1 - 0 0
0:4:2:6 0 - - 0
0:4:8:12 - - 0 0
0:8 - 0 0 0
4:12 - 1 0 0
6:14 - 1 1 0
0:8:4:12 - - 0 0
4:12:6:14 - 1 - 0
8:9 1 0 0 -
6:7 0 1 1 -
0:2:4:6 0 - - 0
4:6:12:14 - 1 - 0
0:4:2:6 0 - - 0
0:4:8:12 - - 0 0
0:8:4:12 - - 0 0
4:12:6:14 - 1 - 0
8:9 1 0 0 -
6:7 0 1 1 -
0:2:4:6 0 - - 0
0:4:8:12 - - 0 0
4:12:6:14 - 1 - 0
0 2 4 6 7 8 9 12 14
8:9 * *
6:7 * *
0:2:4:6 * * * *
0:4:8:12 * * * *
4:12:6:14 * * * *
0 0 0 0 0 1
2 0 0 1 0 1
4 0 1 0 0 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
12 1 1 0 0 1
14 1 1 1 0 1
0 2 4 6 7 8 9 12 14
8:9 * * p
6:7 * * p
0:2:4:6 * * * * p
0:4:8:12 * * * *
4:12:6:14 * * * * p
0 2 4 6 7 8 9 12 14
8:9 * * p
6:7 * * p
0:2:4:6 * * * * p
4:12:6:14 * * * * p
8:9 1 0 0 -
6:7 0 1 1 -
0:2:4:6 0 - - 0
4:12:6:14 - 1 - 0
y <= (x3 and not x2 and not x1) or
(not x3 and x2 and x1) or
(not x3 and not x0) or
(x2 and not x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240612 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240612 is
begin
y <= (x3 and not x2 and not x1) or
(not x3 and x2 and x1) or
(not x3 and not x0) or
(x2 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240612testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240612testbench is
component quine20240612
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240612 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240612 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240612 is
begin
y <= (x3 and not x2 and not x1) or
(not x3 and x2 and x1) or
(not x3 and not x0) or
(x2 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240612testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240612testbench is
component quine20240612
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240612 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;