2025-07-18 ...before ...ghdl20250701.txt

(C) David Vajda
Tue Jul  1 10:51:37 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		0
 2	0	1	0		1
 3	0	1	1		1
 4	1	0	0		1
 5	1	0	1		1
 6	1	1	0		0
 7	1	1	1		1


	x2	x1	x0		y
 2	0	1	0		1
 3	0	1	1		1
 4	1	0	0		1
 5	1	0	1		1
 7	1	1	1		1


	x2	x1	x0		y
Gruppe 1:
 2	0	1	0		1
 4	1	0	0		1
Gruppe 2:
 3	0	1	1		1
 5	1	0	1		1
Gruppe 3:
 7	1	1	1		1


2:3         0   1   -
4:5         1   0   -
3:7         -   1   1
5:7         1   -   1


        2   3   4   5   7
2:3     +   +
4:5             +   +
3:7         +           +
5:7                 +   +


        2   3   4   5   7
2:3     +   +
4:5             +   +
3:7         +           +

2:3         0   1   -
4:5         1   0   -
3:7         -   1   1


    y   <=  (not x2 and x1) or
            (x2 and not x1) or
            (x1 and x0);


library ieee;
use ieee.std_logic_1164.all;

entity quine20250701 is
port (
    x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture behaviour of quine20250701 is
begin
    y   <=  (not x2 and x1) or
            (x2 and not x1) or
            (x1 and x0);

end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250701testbench is
port (
    y: out std_logic
);
end;

architecture behaviour of quine20250701testbench is
    component quine20250701
    port (
        x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
    signal x2, x1, x0: std_logic;
begin
    q: quine20250701 POST MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);