quine20250726.vhdl

-- (C) David Vajda
-- Sat Jul 26 19:00:48 2025
-- 3 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine20250726 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250726 is
begin
	y	<=	(not x2 and not x1) or
			(not x2 and x0) or
			(not x1 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250726testbench is
port (
	y: inout std_logic
);
end;

architecture behaviour of quine20250726testbench is
	component quine20250726
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250726 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);
	x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;
end;