quine20250731.txt

(C) David Vajda
Wed Jul 30 08:55:29 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		1
 2	0	1	0		0
 3	0	1	1		1
 4	1	0	0		0
 5	1	0	1		1
 6	1	1	0		1
 7	1	1	1		1


	x2	x1	x0		y
 1	0	0	1		1
 3	0	1	1		1
 5	1	0	1		1
 6	1	1	0		1
 7	1	1	1		1

 	x2	x1	x0		y
Gruppe 1:
 1	0	0	1		1
Gruppe 2:
 3	0	1	1		1
 5	1	0	1		1
 6	1	1	0		1
Gruppe 3:
 7	1	1	1		1

1:3			0	-	1
1:5			-	0	1
3:7			-	1	1
5:7			1	-	1
6:7			1	1	-


Gruppe 1:
1:3			0	-	1
1:5			-	0	1
Gruppe 2:
3:7			-	1	1
5:7			1	-	1
6:7			1	1	-


Gruppe 1:
1:3			0	-	1
5:7			1	-	1

1:3:5:7			-	-	1

1:5			-	0	1
3:7			-	1	1

1:5:3:7			-	-	1

Gruppe 2:
6:7			1	1	-


1:5:3:7			-	-	1
6:7				1	1	-

	y	<=	(not x0) or
				(x2 and x1);

library ieee;
use ieee.std_logic_1164.all;

entity quine20250730 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250730 is
begin
	y	<=	(not x0) or
				(x2 and x1);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250730testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250730testbench is
	component quine20250730
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250730 POST MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);