quine20250817.vhd

-- (C) David Vajda
-- Sun Aug 17 13:45:17 2025
-- 3 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine20250817 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic;
	c: in std_logic
);
end;

architecture behaviour of quine20250817 is
begin
		y	<=	((not x2 and x0) or
				(not x2 and x1) or
				(not x2 and x1 and x0) and not c) or
				((not x2 and (x1 or x0)) and c);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250817testbench is
port (
	c: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250817testbench is
	component quine20250817
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic;
		c: in std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250817 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y, c=>c);