quine20250830.txt

(C) David Vajda
Sat Aug 30 11:50:02 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		1
 2	0	1	0		0
 3	0	1	1		1
 4	1	0	0		0
 5	1	0	1		1
 6	1	1	0		0
 7	1	1	1		1


	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		1
 3	0	1	1		1
 5	1	0	1		1
 7	1	1	1		1

	x2	x1	x0		y
Gruppe 0:
 0	0	0	0		1
Gruppe 1:
 1	0	0	1		1
Gruppe 2:
 3	0	1	1		1
 5	1	0	1		1
Gruppe 3:
 7	1	1	1		1


0:1			0	0	-
1:3			0	-	1
1:5			-	0	1
3:7			-	1	1
5:7			1	-	1


0:1			0	0	-
1:3			0	-	1
5:7			1	-	1
1:5			-	0	1
3:7			-	1	1


0:1				0	0	-
1:3			0	-	1
5:7			1	-	1
1:3:5:7			-	-	1
1:5			-	0	1
3:7			-	1	1
1:5:3:7			-	-	1

0:1				0	0	-
1:3:5:7			-	-	1
1:5:3:7			-	-	1


Primimplikantentafel:
			0	1	3	5	7
0:1			+	+
1:3:5:7			+	+	+	+
1:5:3:7			+	+	+	+


0:1				0	0	-
1:3:5:7			-	-	1


	y	<=	(not x2 and not x1) or x0;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250830 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250830 is
begin
	y	<=	(not x2 and not x1) or x0;
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250830testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250830testbench is
	component quine20250830
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250830 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);