2025-07-18 ...before ...vhdl3network20250716.txt

(C) David Vajda
Wed Jul 16 13:29:38 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		1
 2	0	1	0		1
 3	0	1	1		0
 4	1	0	0		1
 5	1	0	1		0
 6	1	1	0		0
 7	1	1	1		0


 	x2	x1	x0		y
 1	0	0	1		1
 2	0	1	0		1
 4	1	0	0		1

    y   <=  (not x2 and not x1 and x0) or
            (not x2 and x1 and not x0) or
            (x2 and not x1 and not x0);

library ieee;
use ieee.std_logic_1164.all;

entity quine20250716 is
port (
    x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture behaviour of quine20250716 is
begin
    y   <=  (not x2 and not x1 and x0) or
            (not x2 and x1 and not x0) or
            (x2 and not x1 and not x0);
end;

library ieee;
use ieee.std_logic_1164.all;

architecture behaviour of quine20250716testbench is
    component quine20250716
    port (
        x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
begin
    signal x2, x1, x0: std_logic;

    q: quine20250716 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);