Fr 26. Sep 10:59:59 CEST 2025/quine20250915.txt

(C) David Vajda
Mon Sep 15 18:29:46 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		0
 2	0	1	0		1
 3	0	1	1		1
 4	1	0	0		0
 5	1	0	1		1
 6	1	1	0		0
 7	1	1	1		0


	x2	x1	x0		y
 0	0	0	0		1
 2	0	1	0		1
 3	0	1	1		1
 5	1	0	1		1


	x2	x1	x0		y
Gruppe 0:
 0	0	0	0		1
Gruppe 1:
 2	0	1	0		1
Gruppe 2:
 3	0	1	1		1
 5	1	0	1		1


0:2			0	-	0
2:3			0	1	-
5			1	0	1

		0	2	3	5
0:2		+	+
2:3			+	+
5					+


0:2			0	-	0
2:3			0	1	-
5			1	0	1


	y	<=	(not x2 and not x0) or
			(not x2 and x1) or
			(x2 and not x1 and x0);

-- (C) David Vajda
-- Mon Sep 15 18:29:46 2025
-- 3 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine20250915 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250915 is
begin
	y	<=	(not x2 and not x0) or
			(not x2 and x1) or
			(x2 and not x1 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250915testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250915testbench is
	component quine20250915
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250915 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);