Fr 26. Sep 10:59:59 CEST 2025/quine20250923.vhd

-- (C) David Vajda
-- Tue Sep 23 11:22:50 2025
-- 3 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine20250923 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250923 is
begin
	y	<=	(not x2 and not x1) or
			(x2 and x1) or
			(not x1 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250923testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250923testbench is
	component quine20250923
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250923 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);