Fr 26. Sep 10:59:59 CEST 2025/quine3net092425.txt

(C) David Vajda
Wed Sep 24 11:35:09 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		0
 2	0	1	0		1
 3	0	1	1		0
 4	1	0	0		0
 5	1	0	1		0
 6	1	1	0		1
 7	1	1	1		0



	x2	x1	x0		y
 0	0	0	0		1
 2	0	1	0		1
 6	1	1	0		1


	x2	x1	x0		y
Gruppe 0:
 0	0	0	0		1
Gruppe 1:
 2	0	1	0		1
Gruppe 2:
 6	1	1	0		1

 0:2		0	-	0
 2:6		-	1	0

ok ...

	y	<=	(not x2 and not x0) or
			(x1 and not x0);

-- (C) David Vajda
-- Wed Sep 24 11:35:09 2025
-- 3 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine092425 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine092425 is
begin
	y	<=	(not x2 and not x0) or
			(x1 and not x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine092425testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine092425testbench is
	component quine092425
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine092425 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);