Nächste Seite: Fr 26. Sep 10:59:59 Aufwärts: trixie13ofmyexcersize Vorherige Seite: Fr 26. Sep 10:59:59
(C) David Vajda
Sat Sep 13 08:27:42 2025
4 Network - TTL - Disjunktive Normalform
0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
0 0 0 0 0 1
2 0 0 1 0 1
4 0 1 0 0 1
5 0 1 0 1 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
2 0 0 1 0 1
4 0 1 0 0 1
Gruppe 2:
5 0 1 0 1 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
0:2 0 0 - 0
0:4 0 - 0 0
2:10 - 0 1 0
4:5 0 1 0 -
4:12 - 1 0 0
4:5 0 1 0 -
0:2 0 0 - 0
0:4 0 - 0 0
2:10 - 0 1 0
4:12 - 1 0 0
0 2 4 5 10 12
4:5 + +
0:2 + +
0:4 + +
2:10 + +
4:12 + +
0 2 4 5 10 12
4:5 + +
0:4 + +
2:10 + +
4:12 + +
4:5 0 1 0 -
0:4 0 - 0 0
2:10 - 0 1 0
4:12 - 1 0 0
y <= (not x3 and x2 and not x1) or
(not x3 and not x1 and not x0) or
(not x2 and x1 and not x0) or
(x2 and not x1 and not x0);
-- (C) David Vajda
-- Sat Sep 13 08:27:42 2025
-- 4 Network - TTL - Disjunktive Normalform
library ieee;
use ieee.std_logic_1164.all;
entity quine20250913 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20250913 is
begin
y <= (not x3 and x2 and not x1) or
(not x3 and not x1 and not x0) or
(not x2 and x1 and not x0) or
(x2 and not x1 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20250913testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20250913testbench is
component quine20250913
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20250913 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);