2025-04-23 - quine20250415.txt

(C) David Vajda
Tue Apr 15 11:09:03 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		0
 2	0	1	0		0
 3	0	1	1		1
 4	1	0	0		1
 5	1	0	1		1
 6	1	1	0		1
 7	1	1	1		1


	x2	x1	x0		y
 3	0	1	1		1
 4	1	0	0		1
 5	1	0	1		1
 6	1	1	0		1
 7	1	1	1		1


	x2	x1	x0		y
Gruppe 1:
 4	1	0	0		1
Gruppe 2:
 3	0	1	1		1
 5	1	0	1		1
 6	1	1	0		1
Gruppe 3:
 7	1	1	1		1

4:5			1	0	-
4:6			1	-	0
3:7			-	1	1
5:7			1	-	1
6:7+		1	1	-


3:7			-	1	1
4:6			1	-	0
5:7			1	-	1
4:5			1	0	-
6:7			1	1	-

Gruppe 2:
3:7			-	1	1

Gruppe 1:
4:6			1	-	0
Gruppe 2:
5:7			1	-	1

4:6:5:7			1	-	-

Gruppe 1:
4:5			1	0	-
Gruppe 2:
6:7			1	1	-

4:5:6:7			1	-	-



3:7				-	1	1
4:6:5:7			1	-	-


	y	<=	(x1 and x0) or x2;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250415 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250415 is
begin
	y	<=	(x1 and x0) or x2;
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250415testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250415testbench is
	component quine20250415
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250415 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);