So 20. Apr 12:48:37 CEST 2025 - quine txt

 
(C) David Vajda
Sat Apr 19 17:48:30 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		1
 2	0	1	0		1
 3	0	1	1		1
 4	1	0	0		0
 5	1	0	1		0
 6	1	1	0		0
 7	1	1	1		1


	x2	x1	x0		y
 1	0	0	1		1
 2	0	1	0		1
 3	0	1	1		1
 7	1	1	1		1


	x2	x1	x0		y
Gruppe 1:
 1	0	0	1		1
 2	0	1	0		1
Gruppe 2:
 3	0	1	1		1
Gruppe 3:
 7	1	1	1		1

1:3			0	-	1
2:3			0	1	-
3:7			-	1	1


2:3			0	1	-
1:3			0	-	1
3:7			-	1	1


		1	2	3	7
2:3			+	+
1:3		+		+
3:7				+	+



		1	2	3	7
2:3			+	+			p
1:3		+		+			p
3:7				+	+		p


2:3			0	1	-
1:3			0	-	1
3:7			-	1	1

	y	<=	(not x2 and x1) or
			(not x2 and x0) or
			(x1 and x0);


library ieee;
use ieee.std_logic_1164.all;

entity quine20250419 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250419 is
begin
	y	<=	(not x2 and x1) or
			(not x2 and x0) or
			(x1 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250419testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250419testbench is
	component quine20250419
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250419 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);