Nächste Seite: VHDL-Code Aufwärts: 2024-11-08 Vorherige Seite: 2024-11-08
0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 0
4 0 1 0 0 1
7 0 1 1 1 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
13 1 1 0 1 1
Gruppe 1:
4 0 1 0 0 1
Gruppe 2:
9 1 0 0 1 1
10 1 0 1 0 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
13 1 1 0 1 1
4 0 1 0 0
9:11 1 0 - 1
9:13 1 - 0 1
10:11 1 0 1 -
7 0 1 1 1
4 0 1 0 0
10:11 1 0 1 -
9:11 1 0 - 1
9:13 1 - 0 1
7 0 1 1 1
4 7 9 10 11 13
4 +
10:11 + +
9:11 + +
9:13 + +
7 +
Alle Zeilen?
4 0 1 0 0 1
7 0 1 1 1 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
13 1 1 0 1 1
4 7 9 10 11 13
4 + p
10:11 + + p
9:11 + +
9:13 + + p
7 + p
4 7 9 10 11 13
4 + p
10:11 + + p
9:13 + + p
7 + p
4 0 1 0 0
10:11 1 0 1 -
9:13 1 - 0 1
7 0 1 1 1
y <= (not x3 and x2 and not x1 and not x0) or
(x3 and not x2 and x1) or
(x3 and not x1 and x0) or
(not x3 and x2 and x1 and x0);
y <= not (
(x3 or not x2 or x1 or x0) and
(not x3 or x2 or not x1) and
(not x3 or x1 or not x0) and
(x3 or not x2 or not x1 or not x0);
);
library ieee;
use ieee.std_logic_1164.all;
entity quine20241108 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20241108 is
begin
y <= (not x3 and x2 and not x1 and not x0) or
(x3 and not x2 and x1) or
(x3 and not x1 and x0) or
(not x3 and x2 and x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20241108_testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20241108_testbench is
component quine20241108
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20241108 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);