(C) David Vajda Thu Dec 26 14:10:36 2024 3 Network - TTL - Disjunktive Normalform x2 x1 x0 y 0 0 0 0 0 1 0 0 1 1 2 0 1 0 1 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 0 7 1 1 1 1 x2 x1 x0 y 1 0 0 1 1 2 0 1 0 1 5 1 0 1 1 7 1 1 1 1 x2 x1 x0 y Gruppe 1: 1 0 0 1 1 2 0 1 0 1 Gruppe 2: 5 1 0 1 1 Gruppe 3: 7 1 1 1 1 1:5 - 0 1 2 0 1 0 5:7 1 - 1 1 2 5 7 1:5 + + 2 + 5:7 + + 1:5 - 0 1 2 0 1 0 5:7 1 - 1 y <= (not x1 and x0) or (not x2 and x1 and not x0) or (x2 and x0); y <= not ( (x1 or not x0) and (x2 or not x1 or x0) and (not x2 or not x0) ); library ieee; use ieee.std_logic_1164.all; entity quine3_ttl_20241226 is port ( x2, x1, x0: in std_logic; y: out std_logic ); end; architecture behaviour of quine3_ttl_20241226 is begin y <= (not x1 and x0) or (not x2 and x1 and not x0) or (x2 and x0); end; library ieee; use ieee.std_logic_1164.all; entity quine3_ttl_20241226testbench is port ( y: out std_logic ); end; architecture behaviour of quine3_ttl_20241226testbench is component quine3_ttl_20241226 port ( x2, x1, x0: in std_logic; y: out std_logic ); end component; signal x2,x1, x0: std_logic; begin q: quine3_ttl_20241226 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y); |
-- (C) David Vajda -- WThu Dec 26 14:10:36 2024 -- 3 Network - TTL - Disjunktive Normalform library ieee; use ieee.std_logic_1164.all; entity quine3_ttl_20241226 is port ( x2, x1, x0: in std_logic; y: out std_logic ); end; architecture behaviour of quine3_ttl_20241226 is begin y <= (not x1 and x0) or (not x2 and x1 and not x0) or (x2 and x0); end; library ieee; use ieee.std_logic_1164.all; entity quine3_ttl_20241226testbench is port ( y: out std_logic ); end; architecture behaviour of quine3_ttl_20241226testbench is component quine3_ttl_20241226 port ( x2, x1, x0: in std_logic; y: out std_logic ); end component; signal x2,x1, x0: std_logic; begin q: quine3_ttl_20241226 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y); x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns; x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns; x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns; end; |