Nächste Seite: quine20241229_3x.txt Aufwärts: 2024-12-24 Vorherige Seite: nasm - CPUID
;; (C) David Vajda
;; Sat Dec 28 2024
;; Quinc Mc Cluskey DNF
0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 0
0 0 0 0 0 1
3 0 0 1 1 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
5 0 1 0 1 1
6 0 1 1 0 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
0:8 - 0 0 0
8:9 1 0 0 -
8:10 1 0 - 0
8:12 1 - 0 0
3:7 0 - 1 1
5:13 - 1 0 1
6:7 0 1 1 -
5:7 0 1 - 1
9:13 1 - 0 1
10:14 1 - 1 0
12:13 1 1 0 -
12:14 1 1 - 0
0:8 - 0 0 0
5:13 - 1 0 1
8:9 1 0 0 -
12:13 1 1 0 -
6:7 0 1 1 -
8:10 1 0 - 0
5:7 0 1 - 1
12:14 1 1 - 0
8:12 1 - 0 0
3:7 0 - 1 1
9:13 1 - 0 1
10:14 1 - 1 0
0:8 - 0 0 0
5:13 - 1 0 1
8:9 1 0 0 -
12:13 1 1 0 -
8:9:12:13 1 - 0 -
8:10 1 0 - 0
12:14 1 1 - 0
8:10:12:14 1 - - 0
5:7 0 1 - 1
3:7 0 - 1 1
8:12 1 - 0 0
9:13 1 - 0 1
10:14 1 - 1 0
8:12:10:14 1 - - 0
8:12:9:13 1 - 0 -
6:7 0 1 1 -
0:8 - 0 0 0
5:13 - 1 0 1
8:9:12:13 1 - 0 -
8:10:12:14 1 - - 0
5:7 0 1 - 1
3:7 0 - 1 1
8:12:10:14 1 - - 0
8:12:9:13 1 - 0 -
6:7 0 1 1 -
0:8 - 0 0 0
5:13 - 1 0 1
8:9:12:13 1 - 0 -
8:12:9:13 1 - 0 -
8:10:12:14 1 - - 0
8:12:10:14 1 - - 0
5:7 0 1 - 1
3:7 0 - 1 1
6:7 0 1 1 -
0:8 - 0 0 0
5:13 - 1 0 1
8:9:12:13 1 - 0 -
8:10:12:14 1 - - 0
5:7 0 1 - 1
3:7 0 - 1 1
6:7 0 1 1 -
0 3 5 6 7 8 9 10 12 13 14
0:8 + +
5:13 + +
8:9:12:13 + + + +
8:10:12:14 + + + +
5:7 + +
3:7 + +
6:7 + +
0 3 5 6 7 8 9 10 12 13 14
0:8 + +
8:9:12:13 + + + +
8:10:12:14 + + + +
6:7 + +
5:7 + +
3:7 + +
0:8 - 0 0 0
8:9:12:13 1 - 0 -
8:10:12:14 1 - - 0
5:7 0 1 - 1
3:7 0 - 1 1
6:7 0 1 1 -
y <= (not x2 and not x1 and not x0) or
(x3 and not x1) or
(x3 and not x0) or
(not x3 and x2 and x0) or
(not x3 and x1 and x0) or
(not x3 and x2 and x1);
library ieee;
use ieee.std_logic_1164.all;
entity quine20241228 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20241228 is
begin
y <= (not x2 and not x1 and not x0) or
(x3 and not x1) or
(x3 and not x0) or
(not x3 and x2 and x0) or
(not x3 and x1 and x0) or
(not x3 and x2 and x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20241228testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20241228testbench is
component quine20241228
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20241228 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
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-- (C) David Vajda
-- Sat Dec 28 08:57:13 2024
-- 4 Network - Disjunktive Normalform
library ieee;
use ieee.std_logic_1164.all;
entity quine20241228 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20241228 is
begin
y <= (not x2 and not x1 and not x0) or
(x3 and not x1) or
(x3 and not x0) or
(not x3 and x2 and x0) or
(not x3 and x1 and x0) or
(not x3 and x2 and x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20241228testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20241228testbench is
component quine20241228
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20241228 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;
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