RS-Latch in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity rs_latch_20241108 is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    qs: inout std_logic
);
end;

architecture behaviour of rs_latch_20241108 is
begin
    q <= (r nor qs);
    qs <= (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity rs_latch_20241108_testbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of rs_latch_20241108_testbench is
    component rs_latch_20241108
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        qs: inout std_logic
    );
    end component;
    signal r, s: std_logic;
begin
    rs: rs_latch_20241108 PORT MAP (r=>r, s=>s, q=>q);
    r <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns;
    s <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns;
end;