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0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 0
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
11 1 0 1 1 1
14 1 1 1 0 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
Gruppe 2
5 0 1 0 1 1
6 0 1 1 0 1
Gruppe 3:
11 1 0 1 1 1
14 1 1 1 0 1
1:5 0 - 0 1
2:6 0 - 1 0
4:5 0 1 0 -
4:6 0 1 - 0
11 1 0 1 1
6:14 - 1 1 0
4:5 0 1 0 -
4:6 0 1 - 0
1:5 0 - 0 1
2:6 0 - 1 0
6:14 - 1 1 0
11 1 0 1 1
1 2 4 5 6 11 14
4:5 + +
4:6 + +
1:5 + +
2:6 + +
6:14 + +
11 +
1 2 4 5 6 11 14
4:5 + +
4:6 + +
1:5 + + p
2:6 + + p
6:14 + + p
11 + p
1 2 4 5 6 11 14
4:6 + +
1:5 + + p
2:6 + + p
6:14 + + p
11 + p
4:6 0 1 - 0
1:5 0 - 0 1
2:6 0 - 1 0
6:14 - 1 1 0
11 1 0 1 1
y <= (not x3 and x2 and not x0) or
(not x3 and not x1 and x0) or
(not x3 and x1 and not x0) or
(x2 and x1 and not x0) or
(x3 and not x2 and x1 and x0);
y <= not (
(x3 or not x2 or x0) and
(x3 or x1 or not x0) and
(x3 or not x1 or x0) and
(not x2 or not x1 or x0) and
(not x3 or x2 or not x1 or not x0);
);
library ieee;
use ieee.std_logic_1164.all;
entity quine20241121 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20241121 is
begin
y <= (not x3 and x2 and not x0) or
(not x3 and not x1 and x0) or
(not x3 and x1 and not x0) or
(x2 and x1 and not x0) or
(x3 and not x2 and x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20241121testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20241121testbench is
component quine20241121
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
VHDL-Code:
library ieee;
use ieee.std_logic_1164.all;
entity quine20241121 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20241121 is
begin
y <= (not x3 and x2 and not x0) or
(not x3 and not x1 and x0) or
(not x3 and x1 and not x0) or
(x2 and x1 and not x0) or
(x3 and not x2 and x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20241121testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20241121testbench is
component quine20241121
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20241121 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;