./vhdl20250304/quine20250121.txt

(C) David Vajda
Tue Jan 21 07:36:56 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		1
 2	0	1	0		0
 3	0	1	1		0
 4	1	0	0		1
 5	1	0	1		0
 6	1	1	0		1
 7	1	1	1		1


	x2	x1	x0		y
 1	0	0	1		1
 4	1	0	0		1
 6	1	1	0		1
 7	1	1	1		1


	x2	x1	x0		y
Gruppe 1:
 1	0	0	1		1
 4	1	0	0		1
Gruppe 2:
 6	1	1	0		1
Gruppe 3:
 7	1	1	1		1

1		0	0	1
4:6		1	-	0
6:7		1	1	-

		1	4	6	7
1		+
4:6			+	+
6:7				+	+

1		0	0	1
4:6		1	-	0
6:7		1	1	-

	y	<=	(not x2 and not x1 and x0) or
			(x2 and not x0) or
			(x2 and x1);

library ieee;
use ieee.std_logic_1164.all;

entity quine20250121 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250121 is
begin
	y	<=	(not x2 and not x1 and x0) or
			(x2 and not x0) or
			(x2 and x1);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250121testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250121testbench is
	component quine20250121
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250121 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);