./vhdl20250304/quine20250125.txt

(C) David Vajda
Sat Jan 25 09:41:50 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		1
 2	0	1	0		0
 3	0	1	1		0
 4	1	0	0		1
 5	1	0	1		1
 6	1	1	0		0
 7	1	1	1		1


	x2	x1	x0		y
 1	0	0	1		1
 4	1	0	0		1
 5	1	0	1		1
 7	1	1	1		1

 1:5		-	0	1
 4:5		1	0	-
 5:7		1	-	1

		1	4	5	7
 1:5	+		+
 4:5		+	+
 5:7			+	+

 1:5		-	0	1
 4:5		1	0	-
 5:7		1	-	1

	y	<=	(not x1 and x0) or
			(x2 and not x1) or
			(x2 and x0);

library ieee;
use ieee.std_logic_1164.all;

entity quine20250125 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250125 is
begin
	y	<=	(not x1 and x0) or
			(x2 and not x1) or
			(x2 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250125testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250125testbench is
	component quine20250125
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250125 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);