./vhdl20250304/quine20250129.vhdl

-- (C) David Vajda
-- Tue Feb 18 09:33:06 2025
-- 3 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine20250218 is
port (
    x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture behaviour of quine20250218 is
begin
    y <=    (not x1 and x0) or
            (x2 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;s

entity quine20250218testbench is
port (
    y: out std_logic
);
end;

architecture behaviour of quine20250218testbench is
    component quine20250218
    port (
        x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
begin
    q: quine20250218 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);