./vhdl20250304/quine20250222.txt

(C) David Vajda
Fri Feb 21 18:33:09 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		1
 2	0	1	0		1
 3	0	1	1		1
 4	1	0	0		1
 5	1	0	1		1
 6	1	1	0		0
 7	1	1	1		0


	x2	x1	x0		y
 1	0	0	1		1
 2	0	1	0		1
 3	0	1	1		1
 4	1	0	0		1
 5	1	0	1		1


	x2	x1	x0		y
Gruppe 1:
 1	0	0	1		1
 2	0	1	0		1
 4	1	0	0		1
Gruppe 2:s
 3	0	1	1		1
 5	1	0	1		1

1:3			0	-	1
1:5			-	0	1
2:3			0	1	-
4:5			1	0	-


1:5			-	0	1
1:3			0	-	1
2:3			0	1	-
4:5			1	0	-



			1	2	3	4	5
1:5			+				+
1:3			+		+
2:3				+	+
4:5						+	+


			1	2	3	4	5
1:3			+		+
2:3				+	+
4:5						+	+

1:3			0	-	1
2:3			0	1	-
4:5			1	0	-

	y	<=	(not x2 and x0) or
			(not x2 and x1) or
			(x2 and not x1);

library ieee;
use ieee.std_logic_1164.all;

entity quine20250222 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250222 is
begin
	y	<=	(not x2 and x0) or
			(not x2 and x1) or
			(x2 and not x1);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250222testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250222testbench is
	component quine20250222
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250222 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);