(C) David Vajda
Tue Mar 4 17:08:33 2025
4 Network - TTL - Disjunktive Normalform
0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 1
3 0 0 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
15 1 1 1 1 1
Gruppe 1:
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
11 1 0 1 1 1
Gruppe 4:
15 1 1 1 1 1
8:9 1 0 0 -
8:10 1 0 - 0
8:12 1 - 0 0
3:11 - 0 1 1
9:11 1 0 - 1
10:11 1 0 1 -
11:15 1 - 1 1
8:9 1 0 0 -
10:11 1 0 1 -
8:10 1 0 - 0
9:11 1 0 - 1
8:12 1 - 0 0
11:15 1 - 1 1
3:11 - 0 1 1
Gruppe 1:
8:9 1 0 0 -
Gruppe 2:
10:11 1 0 1 -
Gruppe 1:
8:10 1 0 - 0
Gruppe 2:
9:11 1 0 - 1
8:12 1 - 0 0
11:15 1 - 1 1
3:11 - 0 1 1
Gruppe 1:
8:9 1 0 0 -
Gruppe 2:
10:11 1 0 1 -
8:9:10:11 1 0 - -
Gruppe 1:
8:10 1 0 - 0
Gruppe 2:
9:11 1 0 - 1
8:10:9:11 1 0 - -
8:12 1 - 0 0
11:15 1 - 1 1
3:11 - 0 1 1
8:9:10:11 1 0 - -
8:12 1 - 0 0
11:15 1 - 1 1
3:11 - 0 1 1
3 8 9 10 11 12 15
8:9:10:11 = = = =
8:12 = =
11:15 = =
3:11 = =
8:9:10:11 1 0 - -
8:12 1 - 0 0
11:15 1 - 1 1
3:11 - 0 1 1
y <= (x3 and not x2) or
(x3 and not x1 and not x0) or
(x3 and x1 and x0) or
(not x2 and x1 and x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240304network4 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240304network4 is
begin
y <= (x3 and not x2) or
(x3 and not x1 and not x0) or
(x3 and x1 and x0) or
(not x2 and x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240304network4testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240304network4testbench is
component quine20240304network4
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240304network4 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
|