./vhdl20250308/quine20250306.txt

(C) David Vajda
Thu Mar  6 09:49:06 2025
4 Network - TTL - Disjunktive Normalform

 0 0 0 0 0    0
 1 0 0 0 1    1
 2 0 0 1 0    1
 3 0 0 1 1    0
 4 0 1 0 0    0
 5 0 1 0 1    0
 6 0 1 1 0    0
 7 0 1 1 1    0
 8 1 0 0 0    0
 9 1 0 0 1    1
10 1 0 1 0    1
11 1 0 1 1    0
12 1 1 0 0    0
13 1 1 0 1    0
14 1 1 1 0    0
15 1 1 1 1    0


 1 0 0 0 1    1
 2 0 0 1 0    1
 9 1 0 0 1    1
10 1 0 1 0    1

Gruppe 1:
 1 0 0 0 1    1
 2 0 0 1 0    1
Gruppe 2:
 9 1 0 0 1    1
10 1 0 1 0    1

1:9         -   0   0   1
2:10        -   0   1   0

primimplikantentafel, minimale restueberdeckung

            1   2   9   10
1:9         +       +
2:10            +       +

1:9         -   0   0   1
2:10        -   0   1   0

    y   <=  (not x2 and not x1 and x0) or
            (not x2 and x1 and not x0);

library ieee;
use ieee.std_logic_1164.all;

entity quine20250306 is
port (
    x3, x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture behaviour of quine20250306 is
begin
    y   <=  (not x2 and not x1 and x0) or
            (not x2 and x1 and not x0);

end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250306testbench is
port (
    y: out std_logic
);
end;

architecture behaviour of quine20250306testbench is
    component quine20250306
    port (
        x3, x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
begin
    q: quine20250306 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);