./vhdl20250308/quine3network20250308.txt

(C) David Vajda
Sat Mar  8 08:56:42 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		0
 2	0	1	0		1
 3	0	1	1		1
 4	1	0	0		0
 5	1	0	1		1
 6	1	1	0		1
 7	1	1	1		0


	x2	x1	x0		y
 2	0	1	0		1
 3	0	1	1		1
 5	1	0	1		1
 6	1	1	0		1



 	x2	x1	x0		y
Gruppe 1:
 2	0	1	0		1
Gruppe 2:
 3	0	1	1		1
 5	1	0	1		1
 6	1	1	0		1

2:3			0	1	-
2:6			-	1	0
5			1	0	1

		2	3	5	6
2:3		+	+
2:6		+			+
5				+


2:3			0	1	-
2:6			-	1	0
5			1	0	1

	y	<=	(not x2 and x1) or
			(x1 and not x0) or
			(x2 and not x1 and x0);

library ieee;
use ieee.std_logic_1164.all;

entity quine20250308 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250308 is
begin
	y	<=	(not x2 and x1) or
			(x1 and not x0) or
			(x2 and not x1 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250308testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250308testbench is
	component quine20250308
	port (
		x2, x1, x0: in std_logic;
		y: out std_logics
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250308 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);