Nächste Seite: ./vhdl20250308/quine4network20250307.vhdl Aufwärts: Übungen Vorherige Seite: ./vhdl20250308/quine3network20250308.vhdl
(C) David Vajda
Fri Mar 7 08:10:22 2025
4 Network - TTL - Disjunktive Normalform
0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 0
0 0 0 0 0 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
8 1 0 0 0 1
Gruppe 2:
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
11 1 0 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
0:8 - 0 0 0
8:9 1 0 0 -
8:10 1 0 - 0
8:12 1 - 0 0
9:11 1 0 - 1
9:13 1 - 0 1
10:11 1 0 1 -
10:14 1 - 1 0
12:13 1 1 0 -
12:14 1 1 - 0
8:9 1 0 0 -
10:11 1 0 1 -
12:13 1 1 0 -
8:10 1 0 - 0
9:11 1 0 - 1
12:14 1 1 - 0
8:12 1 - 0 0
9:13 1 - 0 1
10:14 1 - 1 0
0:8 - 0 0 0
Gruppe 1:
8:9 1 0 0 -
Gruppe 2:
10:11 1 0 1 -
12:13 1 1 0 -
Gruppe 1:
8:10 1 0 - 0
Gruppe 2:
9:11 1 0 - 1
12:14 1 1 - 0
Gruppe 1:
8:12 1 - 0 0
Gruppe 2:
9:13 1 - 0 1
10:14 1 - 1 0
0:8 - 0 0 0
Gruppe 1:
8:9 1 0 0 -
Gruppe 2:
10:11 1 0 1 -
12:13 1 1 0 -
8:9:10:11 1 0 - -
8:9:12:13 1 - 0 -
Gruppe 1:
8:10 1 0 - 0
Gruppe 2:
9:11 1 0 - 1
12:14 1 1 - 0
8:10:9:11 1 0 - -
8:10:12:14 1 - - 0
Gruppe 1:
8:12 1 - 0 0
Gruppe 2:
9:13 1 - 0 1
10:14 1 - 1 0
8:12:9:13 1 - 0 -
8:12:10:14 1 - - 0
0:8 - 0 0 0
8:9:10:11 1 0 - -
8:9:12:13 1 - 0 -
8:10:9:11 1 0 - -
8:10:12:14 1 - - 0
8:12:9:13 1 - 0 -
8:12:10:14 1 - - 0
0:8 - 0 0 0
8:9:10:11 1 0 - -
8:10:9:11 1 0 - -
8:9:12:13 1 - 0 -
8:12:9:13 1 - 0 -
8:10:12:14 1 - - 0
8:12:10:14 1 - - 0
0:8 - 0 0 0
8:9:10:11 1 0 - -
8:9:12:13 1 - 0 -
8:10:12:14 1 - - 0
0:8 - 0 0 0
0 8 9 10 11 12 13 14
8:9:10:11 + + + +
8:9:12:13 + + + +
8:10:12:14 + + + +
0:8 + +
8:9:10:11 1 0 - -
8:9:12:13 1 - 0 -
8:10:12:14 1 - - 0
0:8 - 0 0 0
y <= (x3 and not x2) or
(x3 and not x1) or
(x3 and not x0) or
(not x2 and not x1 and not x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20250307 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20250307 is
begin
y <= (x3 and not x2) or
(x3 and not x1) or
(x3 and not x0) or
(not x2 and not x1 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20250307testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20250307testbench is
component quine20250307
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20250307 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
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