quine20250314.txt

(C) David Vajda
Fri Mar 14 14:42:22 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		0
 2	0	1	0		0
 3	0	1	1		1
 4	1	0	0		1
 5	1	0	1		0
 6	1	1	0		1
 7	1	1	1		1


 	x2	x1	x0		y
 0	0	0	0		1
 3	0	1	1		1
 4	1	0	0		1
 6	1	1	0		1
 7	1	1	1		1

Gruppe 0:
 0	0	0	0		1
Gruppe 1:
 4	1	0	0		1
Gruppe 2:
 3	0	1	1		1
 6	1	1	0		1
Gruppe 3:
 7	1	1	1		1

0:4			-	0	0
4:6			1	-	0
3:7			-	1	1
6:7			1	1	-



0:4			-	0	0
3:7			-	1	1
4:6			1	-	0
6:7			1	1	-


		0	3	4	6	7
0:4		+		+
3:7			+			+
4:6				+	+
6:7					+	+


		0	3	4	6	7
0:4		+		+
3:7			+			+
4:6				+	+


0:4			-	0	0
3:7			-	1	1
4:6			1	-	0

	y	<=	(not x1 and not x0) ot
			(x1 and x0) or
			(x2 and not x0);

library ieee;
use ieee.std_logic_1164.all;

entity quine20250314 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250314 is
begin
	y	<=	(not x1 and not x0) ot
			(x1 and x0) or
			(x2 and not x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250314testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250314testbench is
	component quine20250314
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250314 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);



	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		0
 2	0	1	0		0
 3	0	1	1		1
 4	1	0	0		1
 5	1	0	1		0
 6	1	1	0		1
 7	1	1	1		1


	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		0
 2	0	1	0		0
 3	0	1	1		1
 4	1	0	0		1
 5	1	0	1		0
 6	1	1	0		1
 7	1	1	1		1


 3	0	1	1		1
 4	1	0	0		1
 6	1	1	0		1
 7	1	1	1		1

Gruppe 1:
 4	1	0	0		1
Gruppe 2:
 3	0	1	1		1
 6	1	1	0		1
Gruppe 3:s
 7	1	1	1		1

4:6		1	-	0
3:7		-	1	1
6:7		1	1	-


6:7		1	1	-
4:6		1	-	0
3:7		-	1	1