quine20250316.txt

(C) David Vajda
Sun Mar 16 15:01:10 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		1
 2	0	1	0		0
 3	0	1	1		0
 4	1	0	0		0
 5	1	0	1		1
 6	1	1	0		1
 7	1	1	1		0


	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		1
 5	1	0	1		1
 6	1	1	0		1


	x2	x1	x0		y
Gruppe 0:
 0	0	0	0		1
Gruppe 1:
 1	0	0	1		1
Gruppe 2:
 5	1	0	1		1
 6	1	1	0		1

0:1			0	0	-
1:5			-	0	1
6			1	1	0


		0	1	5	6
0:1		+	+
1:5			+	+
6					+


0:1			0	0	-
1:5			-	0	1
6			1	1	0

	y	<=	(not x2 and not x1) or
			(not x1 and x0) or
			(x2 and x1 and not x0);

library ieee;
use ieee.std_logic_1164.all;

entity quine20250316 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20250316 is
begin
	y	<=	(not x2 and not x1) or
			(not x1 and x0) or
			(x2 and x1 and not x0);
end;

library ieee;
use ieee.std_logic_1164.all;s

entity quine20250316testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20250316testbench is
	component quine20250316
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250316 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);


	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		1
 5	1	0	1		1
 6	1	1	0		1
 7	1	1	1		1

Gruppe 0:
 0	0	0	0		1
Gruppe 1:
 1	0	0	1		1
Gruppe 2:
 5	1	0	1		1
 6	1	1	0		1
Gruppe 3:
 7	1	1	1		1

0:1			0	0	-
1:5			-	0	1
5:7			1	-	1
6:7			1	1	-

0:1			0	0	-
6:7			1	1	-
5:7			1	-	1
1:5			-	0	1

		0	1	5	6	7
0:1		+	+
6:7					+	+
5:7				+		+
1:5			+	+

		0	1	5	6	7
0:1		+	+
6:7					+	+
5:7				+		+

0:1			0	0	-
6:7			1	1	-
5:7			1	-	1

		0	1	5	6	7
0:1		+	+
6:7					+	+
1:5			+	+

0:1			0	0	-
6:7			1	1	-
1:5			-	0	1


0:1			0	0	-
1:5			-	0	1
6			1	1	0