MIPS32 in VHDL

Post by **david** » Mon Dec 02, 2024 8:22 am

32 Bit Ripple Carry Chain Addierer

-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02

library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
port (
    a: in std_logic;
    b: in std_logic;
    c: out std_logic;
    s: in std_logic;
    t: out std_logic
);
end;

architecture behaviour of fulladder is
begin
    c <= a xor b xor s;
    t <= (a and b) or ((a or b) and s);
end;

library ieee;
use ieee.std_logic_1164.all;

entity ripplecarrychainadder32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    s: in std_logic;
    t: out std_logic
);
end;

architecture behaviour of ripplecarrychainadder32 is
    component fulladder
    port (
        a: in std_logic;
        b: in std_logic;
        c: out std_logic;
        s: in std_logic;
        t: out std_logic
    );
    end component;
    signal x: std_logic_vector (32 downto 0);
begin
        fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
            fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
        END GENERATE;
        t <= x (32) ;
        x (0) <= s;
    --fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
    --fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
    --fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
    --fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;

library ieee;
use ieee.std_logic_1164.all;

entity ripplecarrychainadder32testbench is
port (
    c: out std_logic_vector (31 downto 0);
    t: out std_logic
);
end;


architecture behaviour of ripplecarrychainadder32testbench is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    signal a: std_logic_vector (31 downto 0);
    signal b: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    rplcadd: ripplecarrychainadder32 PORT MAP (c=>c, b=>b, a=>a, s=>s, t=>t);
    -- 19219 + 14823 = 34042
    -- 0b100101100010011 + 0b11100111100111 = 0b1000010011111010
    a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;

    b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
    s <= '0';
end;

Subtrahierer:

Code: Select all

-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02

library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
port (
    a: in std_logic;
    b: in std_logic;
    c: out std_logic;
    s: in std_logic;
    t: out std_logic
);
end;

architecture behaviour of fulladder is
begin
    c <= a xor b xor s;
    t <= (a and b) or ((a or b) and s);
end;

library ieee;
use ieee.std_logic_1164.all;

entity ripplecarrychainadder32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    s: in std_logic;
    t: out std_logic
);
end;

architecture behaviour of ripplecarrychainadder32 is
    component fulladder
    port (
        a: in std_logic;
        b: in std_logic;
        c: out std_logic;
        s: in std_logic;
        t: out std_logic
    );
    end component;
    signal x: std_logic_vector (32 downto 0);
begin
        fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
            fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
        END GENERATE;
        t <= x (32) ;
        x (0) <= s;
    --fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
    --fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
    --fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
    --fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;

library ieee;
use ieee.std_logic_1164.all;

entity ripplecarrychainadder32testbench is
port (
    c: out std_logic_vector (31 downto 0);
    t: out std_logic
);
end;


architecture behaviour of ripplecarrychainadder32testbench is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    signal a: std_logic_vector (31 downto 0);
    signal b: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    rplcadd: ripplecarrychainadder32 PORT MAP (c=>c, b=>b, a=>a, s=>s, t=>t);
    -- 19219 + 14823 = 34042
    -- 0b100101100010011 + 0b11100111100111 = 0b1000010011111010
    a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;

    b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
    s <= '0';
end;

library ieee;
use ieee.std_logic_1164.all;

entity com32 is
port (
    x: in std_logic_vector (31 downto 0);
    y: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of com32 is
begin
        com_connect: FOR i IN 31 DOWNTO 0 GENERATE
                y (i) <= not x (i);
        END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity neg32 is
port (
    b: out std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    t: out std_logic
);
end;

architecture behaviour of neg32 is
    component com32
    port (
        x: in std_logic_vector (31 downto 0);
        y: out std_logic_vector (31 downto 0)
    );
    end component;

    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    signal c: std_logic_vector (31 downto 0);
    signal d: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    neg32_generate_1: FOR i IN 31 DOWNTO 0 GENERATE
        d (i) <= '0';
    END GENERATE;
    s <= '1';
    com: com32 PORT MAP (x=>a, y=>c);
    add: ripplecarrychainadder32 PORT MAP (b=>d, a=>c, s=>s, t=>t, c=>b);
end;

library ieee;
use ieee.std_logic_1164.all;

entity sub32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    t: out std_logic
);
end;

architecture behaviour of sub32 is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component neg32
    port (
        b: out std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    signal x: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    neg: neg32 PORT MAP (a=>a, b=>x);
    add: ripplecarrychainadder32 PORT MAP (b=>b, a=>x, c=>c, s=>s, t=>t);
    s <= '0';
end;

library ieee;
use ieee.std_logic_1164.all;

entity sub32testbench is
port (
    c: out std_logic_vector (31 downto 0);
    t: out std_logic
);
end;


architecture behaviour of sub32testbench is
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    signal a: std_logic_vector (31 downto 0);
    signal b: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    sub: sub32 PORT MAP (a=>a, b=>b, c=>c, t=>t);

    a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
    b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns,  ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
    s <= '0' after 0 ns, '1' after 10 ns;
    -- 19219 - 14823 =
end;

19219 - 14823 = 4396 ^= 0x112C
14823 - 19219 = -4396 ^= 0xFFFFFFFFFFFFEED4

Post by **david** » Mon Dec 02, 2024 1:00 pm

als, naechstes brauche ich einen 32x2:1 MUX, kein Problem. Beim Registersatz kaskadiere ich Einen Registersatz mit 2 zu 4. Zu 8...

man braucht keinen komperator - weil vergleiche gibt es nur bei verzweigungsbefehlen sonst machen sie keinen sinn - im gegensatz zu intels - cmp und dann bedingter verzweigung je, jne, jg, jng, ... gibt es bei mips32 breq, brne, brgt, brge .. >, <, =, ... das alles geht mit Subtraktion. Selbst cmp koennte so gemacht werden. Wichtig ist, ob das Ergebnis 0 ist. Dann sind beide operanden gleich, das kann man mit einfachen NOR testen. Bei negativen Ergebnissen werden entsprechend Carry flag und so weiter gesetzt sein. So erreichen wir vergleiche, <, ... durch Subtraktion

Entschuldigung NAND war natuerlich Unsinn, NOR

Code: Select all

OR 
0, 0, 0
0, 1, 1
1, 0, 1
1, 1, 1

Code: Select all

NOR
0, 0, 1
1, 0, 0
0, 1, 0
1, 1, 0

man braucht keinen komperator - weil vergleiche gibt es nur bei verzweigungsbefehlen sonst machen sie keinen sinn - im gegensatz zu intels - cmp und dann bedingter verzweigung je, jne, jg, jng, ... gibt es bei mips32 breq, brne, brgt, brge .. >, <, =, ... das alles geht mit Subtraktion. Selbst cmp koennte so gemacht werden. Wichtig ist, ob das Ergebnis 0 ist. Dann sind beide operanden gleich, das kann man mit einfachen NOR testen. Bei negativen Ergebnissen werden entsprechend Carry flag und so weiter gesetzt sein. So erreichen wir vergleiche, <, ... durch Subtraktion
man braucht NAND eher selten. Man braucht XOR und NOR - NOR um zu gucken, sind alle Null, XOR fuer Paritaet. ist die Paritaet ungerade, dann liefert 0, 0 => 0, und 1, 1 => 0, sonst 1, bei der gerade Paritaet brauchen wir ein invertiertes NOR? Nein, natuerlich nicht. Bei der Ungaraden haengen wir ein weiteres, bit an, ebenso bei der geraden. ein Mal aber gesetzt ein mal nicht

jetzt der MUX auch nicht schwer

32 Bit x 2:1 MUX
heisst es richtig.

viel mehr ausser dem MUX, wir brauchen 4 MUX ausserhalb der ALU und dem Registersatz und diesen ist nicht zu tun. Fuer unseren MIPS32, der Befehlsdekodierer und Funktionsdekodierer, sind lediglich ein Kodierer, der die entsprechenden Steuerbit setzt zum Beispiel fuer die 4 MUX und die ALU und Registersatz, natuerlich brauchen wir Speicher und Programmspeicher, aber das laesst sich mit registern und VHDL Generate und FOR sofort machen. Nicht im Blockschaltbild ist ein E/A Port

es ist ganz einfach von der seriellen Schnittstelle zu TCP/IP zukommen. Damit meine ich kein wenig die Anwendung Schicht aber die zwei unteren Schichten TCP/IP, das geht ganz einfach mit der seriellen Schnittstelle. Sie werden sehen. Ich kann ja ein MIPS 32 in vhdl machen und ich habe eine sehr genauen Vorstellung davon, was eine serielle Schnittstelle ist das habe ich einerseits von den MIPS 32, den ich in vhdl machen will, andererseits auch vom AVR oder überhaupt den sio oder Pio damit ist es kein Problem, nicht mit dem pio aber sio warum? Letztenendes ist Ethernet Ich könnte Ihnen genauso guten Modem nehmen nur eine serielle Schnittstelle, die nicht funktioniert wie die anderen gut und am was unterscheidet eigentlich das ACK/NAK Protokoll des? X-on/x-off Protokoll und dazu noch von dem Hardware nein das ist ganz einfach. Es gibt die Zeichen wenn man den ASC II Code auswendig lernt, dann weiß man, dass es diese Zeichen gibt. Ack/nak dc1 dc3 im entsprechend die Protokolle des bedeutet nichts für die Zeichen. Die werden damit nicht selber synchronisiert weil bei der RS 232 werden immer die Zeichen übertragen. Es ist klar, da steckt im Code wer es benutzt hat wie ich mit dem AVR, der weiß die Zeichen werden sollte so übertragen das dient zur Synchronisierung im gesamten Zeichen Strom wann fängt denn die Nachricht an. Und wann hört sie auf? hat mit den Zeichen selber nichts zu tun so, das ist das eine. Sie können genauso gut ack/nak nehmen, um zu erkennen hier die Nachricht an hier hört sie auf gut und was macht TCP/IP gut in ihren seriellen Zeichen. Strohm müssen Sie nur noch die Dinge erst mal in Pakete zerlegen und entsprechende Kopf- und Fußzeilen anfügen und die Adressen einfügen. TCP/IP hat mit der Anwendung Schicht nichts zu tun. Lediglich ein Router liegt in der Mitte, und um die Adressierung vorzunehmen, gibt es IP und um es in Pakete zu zerlegen, TCP. Gut das ist in einem seriellen Zeichen Strohm relativ einfach. Sie müssen bloß die Pakete nach unten weiterreichen beziehungsweise die Daten und entsprechende Kopf- und Fußzeilen anfügen. Da man ja auswendig lernt, kann man auswendig lernen. Was sind die Pakete rein kann also das dürfte kein Problem sein.

sie brauchen beim Registersatz MUX und DeMUX
nein sorry das war falsch gemacht, ich brauche keinen DeMUX beim Registersatz - das ist Quatsch, sonst werden alle 0. Das ist nicht richtig, was brauche ich denn? ganz einfach, jedes Register hat ein EN - enable - und nur, wenn EN jeweils vom gesamten Registersatz 1 ist schreibt man rein. Aber wie kann ich die Register unterscheiden, hier brauche ich DeMUX und EN. Ich muss nicht den Datenengang, DeMUX sondern, EN am jeweiligen Register

jetzt kommt, der DeMUX und ich mache beides gleich, fuer eine Auswahl von 5 Bit - fuer 32 - durch kaskadierung

nein sorry das war falsch gemacht, ich brauche keinen DeMUX beim Registersatz - das ist Quatsch, sonst werden alle 0. Das ist nicht richtig, was brauche ich denn? ganz einfach, jedes Register hat ein EN - enable - und nur, wenn EN jeweils vom gesamten Registersatz 1 ist schreibt man rein. Aber wie kann ich die Register unterscheiden, hier brauche ich DeMUX und EN. Ich muss nicht den Datenengang, DeMUX sondern, EN am jeweiligen Register

Das ist logisch, sie muessen EN aktivieren, der gesamte registersatz hat einen. Zusaetzlich haben sie ein Zielregister. Bei dem geht es um den Eingang. Das Zielregister wird mittels globalen EN eingeschaltet, indem man ein AND, vom DeMUX, bei der Auswahl des Zielregisters macht, was wiederum ein bit ergibt, also quasi ein EN. Da kommt ein AND rein
Tristates fuer alle die die lieben und das Wort immer wieder gerne wiederholen. Denen sei gesagt, hier gibt es drei Zustaende
HIGH, LOW, Hochohmig
was ist letzteres. Wenn etwas hochohmig ist, dann ist es, als waere es nicht da. Widerstand der Luft. das brauchen sie, wenn sie mehrere Geraete ohne EN aneinanderschalten und zwar mit Ausgaengen. sie koennn beliebig viel abnehmer an eingaengen haben, an ausgaengen ist es toedlich. Sie duerfen ausgaenge, egal, HIGH, LOW nicht verschalten
Das zu untersuchen ist nicht teil des Themas. Es ist unsachlich, pille palle. Hat mit uns nichts zu tun. Wer davon traeumt liegt falsch. Das gibt es innerhalb des Prozessors nicht, weil hier alles zusammenarbeitet. Wer davon traeumt ist hier falsch
Sie koennen das uebrigens auch gebrauchen, wenn sie denselben Bus als eingabe oder Ausgabe Bus gleichzeitig gebrauchen, etwa bei Ports ausserhalb des Prozessors. Dann koennen sie immer die Eingabe hochohmig machen, die einen anderen Pfad hat, als die ausgabe, wenn die ausgabe aktiv ist und umgekehrt
Aber diese Frage stellen sich hier bitte nur leute, die die nummer fuer die anstaltsleitung suchen, solche gibt es leider, viele, deswegen sage ich das, ich kenne solche, das ist natuerlich abwaegig.

Code: Select all

-- (C) David Vajda
-- 32 Bit x 2:1 MUX
-- 2024-12-02

library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1 is
port (
    c: out std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX32_2_1 is
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1testbench is
port (
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of MUX32_2_1testbench is
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal b: std_logic_vector (31 downto 0);
    signal a: std_logic_vector (31 downto 0);
    signal x: std_logic;
begin
    mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);

    a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
    b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
    x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity DeMUX32_2_1 is
port (
    c: in std_logic_vector (31 downto 0);
    b: out std_logic_vector (31 downto 0);
    a: out std_logic_vector (31 downto 0);
    x: in std_logic
);
end;

architecture behaviour of DeMUX32_2_1 is
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        a (i) <= (c (i) and not x);
        b (i) <= (c (i) and x);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity DeMUX32_2_1testbench is
port (
    a: out std_logic_vector (31 downto 0);
    b: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of DeMUX32_2_1testbench is
    component DeMUX32_2_1 is
    port (
        c: in std_logic_vector (31 downto 0);
        b: out std_logic_vector (31 downto 0);
        a: out std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal c: std_logic_vector (31 downto 0);
    signal x: std_logic;
begin
    mux: DeMUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);

    c <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
    x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;

jetzt kommen 5 kaskadierte MUX

Code: Select all

    -- (C) David Vajda
    -- 32 Bit x 2:1 MUX
    -- 2024-12-02

    library ieee;
    use ieee.std_logic_1164.all;

    package MIPS32 is
        type bus2_32 is array (1 downto 0) of std_logic_vector (31 downto 0);
        type bus4_32 is array (1 downto 0) of std_logic_vector (31 downto 0);
    end package;

    library ieee;
    use ieee.std_logic_1164.all;
    library work;
    use work.mips32.all;

    entity MUX32_2_1 is
    port (
        b: out std_logic_vector (31 downto 0);
        a: in bus2_32;
        x: in std_logic
    );
    end;

    architecture behaviour of MUX32_2_1 is
    begin
        MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
            b (i) <= (a (1)(i) and not x) or (a(0) (i) and x);
        END GENERATE;
    end;

    library ieee;
    use ieee.std_logic_1164.all;
    library work;
    use work.mips32.all;

    entity MUX32_4_1 is
    port (
        b: out std_logic_vector (31 downto 0);
        a: in bus4_32;
        x: in std_logic
    );
    end;

architecture behaviour of MUX32_2_1 is
    component MUX32_2_1
    port (
        b: out std_logic_vector (31 downto 0);
        a: in bus2_32;
        x: in std_logic
    );
    end component;
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        b (i) <= (a (1)(i) and not x) or (a(0) (i) and x);
    END GENERATE;
end;

Ich habe es wohl falsch gezeigt. Wir brauchen die Dekodierer kein
und demultiplexer was das EN betrifft, aber das lustige ist ja: doch es geht schon. Das ist genau das, dass es eben schon geht. Wenn wir nämlich genau den DeMUX nehmen und dann an den Eingang eine eins legen und sonst überall null ist
Das, was ich jetzt sagte, stellt meine Intelligenz nicht infrage, weil der Witz ist, ja ein Decoder ist ein Kodierer, der für jede Form von Eingangssignal immer nur je einen Ausgang ein Signal abgeben lässt was Eins ist so, jetzt kann beim Dekoda allerdings jede beliebige Form von Eingangssignal reingehen im Allgemeinen der Unterschied ist, dass der DeMUX konsekutive nummerierte Eingangs Signale hat d.h. ganze Zahlen, und die lassen sich nummerieren die ganze Zahlen und entsprechend dem DeMUX bei dem eine Eins anliegt und sonst überall Null ist
Es besteht manchmal die Verwechslungsgefahr zwischen kodierer, Dekodierer und einem letzten Encoder, Letzteres gebraucht man nicht unbedingt. Der Unterschied ist, der dekodieren ist nicht die inverse Funktion zum Kodierer, das stimmt nicht, sondern hat für einen Ausgang immer nur je ein Signal. Eine Eins, das ist etwas spezielles. Die Umkehrfunktion wäre im Allgemeinen höchstens ein Encoder wenn man so will aber das ist nicht unbedingt richtig
Ich hab mich nicht geirrt mit dem DeMUX keine Sorge. Ist immer noch ein dekoder. der Unterschied ist, dass die Eingangs Signale konsekutiveniert sind. Das ist praktisch das allerdings so zu machen weil das ist genau der selbe Weg nur es lässt sich so realisieren und es ist praktischer so aus einem einzigen Grund man muss halt begreifen, dass dann immer die Signal 1 anliegt, das praktischer das so zu machen weil ein Dekoda lässt sich im Allgemeinen nicht ganz so einfach realisieren. Es ist viel Schreibarbeit ein DeMUX so, wie ich das bisher gemacht habe, eben moscadosiert das entsteht durch das konsekutive nummerierte
Das

Bevor ich jetzt weiter mache, und weiter Suche mache ich heute Abend an dem fpga/vhdl/mips32 weiter jetzt stehen ja gerade an die multiplexer

Das Wort Abel war unsere Zeit damals übrigens gängig, und ich musste sagen, ich hab das nie gelernt. Inzwischen fällt mir auf, wie viele andere wohl auch nicht.

Bei dem Registers Satz bei dem Daten Ausgang 32 Bit bei multiplexer brauche ich wohl doch kein Array, und das aus einem einfachen Grund, aus zwei Registern mit einem multiplexer ein Registersatz von zwei Registern, dann nehme ich zwei solche und habe vier Register, aber da brauche ich kein Bus von jeweils 32 × 32

Demultiplexer brauche ich so nicht. Haben wir ja festgestellt, weil das über en enable geschieht und damit nichts gewonnen wäre, wenn ich das als DeMUX realisieren würde, sonst hätte ich den wert, null, der auch übernommen würde, was er ja nicht soll

Ich muss allerdings den Registersatz sozusagen aus einem Guss machen. Selbstverständlich ist es nicht weil ich muss erst mal darüber nachdenken, wie ich den Registers Satz mache. Der MIPS 32 ist mit dem Block Schalt Bild, was ich habe vollständig beschrieben. Sie dürfen sich nicht in die irre führen lassen der große Blog da oben ist lediglich Kodierer oder Dekodierer das müssen Sie nur ihre Werte umsetzen das ist kein Problem. Es ist allerdings nicht beschrieben, wie der Registers Satz konkret aussieht, innerhalb des Registers Satz also das Block Bild schreibt nicht vor wie ich die mux darin Umsätze ,was wir allerdings wissen müssen. Es gibt zwei Quell Operanden vom Registers Satz. Warum es keinen Sinn macht, die nicht aus einem Guss zu fertigen, weil ich dann noch die en habe für das Zielregister und die würden sonst in der Luft herumhängen dazu kommt, dass ich eben zwei Quell Operanden habe d.h. ich brauche zwei mux gleichzeitig

Also gut multiplexer haben wir bereits ein multiplexer haben. Wir und d Flip Flops haben wir auch bereits. geht's nur noch darum, diese zum Register zu machen das dürfte wie bei dem 32 Bit addiere kein Problem sein und dann geht's drum. Wir brauchen nicht malen Takt. Wir brauchen nicht beides gleichzeitig wie das bei den gekauften so üblich ist oder Sie können auch bei dem gekauften da brauchen Sie nur das CLK benutzen. Manchmal haben die beide sozusagen, aber sie können es CLK für E. N benutzen gut und dann hat sich das ja erledigt Und dann kann man schon mal zwei mit zwei mux die wir ja bereits haben, die einfachen zu einem Registers Satz mit zwei zusammenfassen und die EAN können wir dann bei beiden. Vielleicht führen wir dann doch ein CLK ein, weil sonst immer irgendein aktiviert ist. Wenn nein nein ich hab mich geirrt. Wir brauchen CLK und wir brauchen en der Witz ist, dass wir ja die Auswahl Adresse haben für das Ziel Register.
Und die Auswahl Adresse ist was im Gegensatz zu dem eben DeMUX brauchen wir sozusagen hier das EN aktiviert gut das ist die Adresse unseres Ziel Registers aber wenn wir nur das Ziel Register haben, sozusagen über das Dekoda über die 5 Bit Decoder, dann besteht das Problem, dass wir immer ein Ziel Operanten gleichzeitig aktiv haben. D.h. irgendwo wird reingeschrieben und das wollen wir ja nicht. Wir wollen unter Umständen gar nicht reinschreiben, d.h. wir brauchen hier ein AND und das ist EN dieses ist was sonst? Clk ist, während wir gleichzeitig ein logisches und zu unserem Ziel Register, haben, was kein multiplexer am Eingang ist, sondern eben logisches und mit dem EN, was sonst der Takt ist

So vorstellen Sie haben ein globales E N und das ist nicht jederzeit aktiv an dem Ziel Register liegt so oder so Wert an, wenn sie sich jetzt den einfachsten MIPS 32, wie ich ihn mache vorstellen, dann arbeitet er alles in einem Takt ab. Jeder Befehl dauert einen Takt. Jetzt kann im mips 32 eine fünfstufige Befehlspipeline haben. Auf der anderen Seite, muss nicht in den Registers Satz geschrieben werden. Das Ziel kann genauso gut der Arbeitsspeicher sein also der Datenspeicher ist ja ne Harvard Architektur dann liegt trotzdem ein Wert an dem Ziel Regung. Bistorant wird in den Arbeitsspeicher geschrieben dann würde jetzt trotzdem auch in den Registers Satz geschrieben. Des Befehlsdekoda kann zwar aussuchen, was die Quelle ist am jeweiligen Block. Aber was es nicht kann Es kann die einzelnen Teile, dass sie die Werte übernehmen, also die einzelnen Blöcke nur über das EN am Block sozusagen selber aktivieren. Das andere ist, wenn sie ne fünfstufige Befehlspipeline haben also IF, ID, EX, MEM, W B. Dann wird nur in bestimmten Stufen übernommen, würde das EN nicht existieren dann würde ihn jeder Stufe gleichzeitig einen Wert am Registers Satz übernommen werden.

Jetzt wird es die Aufgabe für heute Abend fange ich einfach an. Ich mach ein Register mit 32 Bit das das hat jetzt erst mal ein EN und dann mache ich ein Registers Satz mit zwei Registern und die haben eben ein en und eine Adresse für das Ziel und zwei mux am Ausgang für den ein Quelloperanten und für den anderen

Zum Beispiel Registers Satz mit zwei Registern haben und dann haben sie eine Adresse mit 1 Bit dies entweder null oder eins. Dann wird entweder in Register null oder in Register eins geschrieben wenn das alles ist. Je nachdem halt ob der Wert an dem Bit eins oder null ist das alles ist und sie kein globales? En haben dann wird in jedem Fall in ein Register geschrieben, weil die Adresse ist entweder null oder eins das geht ja nicht deswegen brauchen Sie globales EN das wird über ein logisches und von dem globalen EN und der Adresse erstellt und das passiert aber erst im Registersatz das ist nicht schon am Register selber vorhanden. Das hat ein einziges CLK was ein EN ist

Code: Select all

-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04

library ieee;
use ieee.std_logic_1164.all;

entity rslatch is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch is
begin
    q   <=  (r nor p);
    p   <=  (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch is
    component rslatch
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, d: std_logic;
begin
    rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
    d <= c and s;
    e <= c and r;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch is
    component clktriggeredrslatch
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatchtestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatchtestbench is
    component dlatch
    port (
        c: in std_logic;
        d: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff is
    component dlatch
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal e, a, b: std_logic;
begin
    d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
    d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
    a <= not c;
    b <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dfftestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dfftestbench is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dff PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

so weit so gut

Code: Select all

-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04

library ieee;
use ieee.std_logic_1164.all;

entity rslatch is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch is
begin
    q   <=  (r nor p);
    p   <=  (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch is
    component rslatch
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, d: std_logic;
begin
    rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
    d <= c and s;
    e <= c and r;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch is
    component clktriggeredrslatch
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatchtestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatchtestbench is
    component dlatch
    port (
        c: in std_logic;
        d: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff is
    component dlatch
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal e, a, b: std_logic;
begin
    d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
    d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
    a <= not c;
    b <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dfftestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dfftestbench is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dff PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity reg32 is
port (
    c: in std_logic;
    d: in std_logic_vector (31 downto 0);
    q: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of reg32 is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal p: std_logic_vector (31 downto 0);
begin
    gen_reg: FOR i in 31 downto 0 generate
        dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
        q(i) <= p (i);
    end generate;
end;

Jetzt der Test, für das 32 mit Register

Übrigens, nachher an dem multiplexer und dem Dekoda sagen wir mal DeMUX immer noch das Problem, dass sie jetzt ABC DE haben bei 5 Bit das macht aber nichts weil wenn der Registersatz mit den 32 Beträge dann erst fertig ist dann können Sie die immer noch einzeln und es sind ja nur 5 Bit das ist kein Problem auf ein Array mit 5 Bit Umsätzen

Code: Select all

-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04

library ieee;
use ieee.std_logic_1164.all;

entity rslatch is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch is
begin
    q   <=  (r nor p);
    p   <=  (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch is
    component rslatch
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, d: std_logic;
begin
    rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
    d <= c and s;
    e <= c and r;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch is
    component clktriggeredrslatch
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatchtestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatchtestbench is
    component dlatch
    port (
        c: in std_logic;
        d: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff is
    component dlatch
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal e, a, b: std_logic;
begin
    d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
    d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
    a <= not c;
    b <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dfftestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dfftestbench is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dff PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity reg32 is
port (
    c: in std_logic;
    d: in std_logic_vector (31 downto 0);
    q: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of reg32 is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal p: std_logic_vector (31 downto 0);
begin
    gen_reg: FOR i in 31 downto 0 generate
        dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
        q(i) <= p (i);
    end generate;
end;

library ieee;
use ieee.std_logic_1164.all;


entity dffregtestbench is
port (
    q: inout std_logic_vector (31 downto 0)
);
end;

architecture behaviour of dffregtestbench is
    component reg32
    port (
        q: out std_logic_vector (31 downto 0);
        d: in std_logic_vector (31 downto 0);
        c: in std_logic
    );
    end component;
    signal d: std_logic_vector (31 downto 0);
    signal c: std_logic;
begin
    r32: reg32 PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

Also das Register tut, wie sie sehen am Test. Was mussten wir beim Testen machen? Wir mussten ja jetzt aus dem 1 Bit Eingabewert beim Register ein 32 Bit Eingabe und Ausgabe Wert machen bis auf bei CLK naja bei einem Bit lauteten konkreter Wert '1' und beim 32 Bit wert sind. 32 Tupel. ('0', '0', ...) wir mussten da einfach ein charakteristischen Wert einsetzen und einmal ein Tupel mit mit dem Wert dem Ganzzahl Wert null und einem anderen und das ergibt es charakteristische Bild hier bei gtkwave

Zwei multiplexer hinten dran, zwei 32:2x1 und eben das en und des regdst das ist ein 5 Bit Wert quasi da steht für Register Destination. Das ist nicht der Eingabe wert beim Ziel Operanten aber das ist die Auswahl von Register Destination. Das müssen wir eben machen und das machen wir auch mit dem demultiplexer wiederum der allerdings dann wie gesagt die Funktion eines Dekoda hat nur das eben bei diesem DeMUX immer der Wert eins anliegt. Dadurch wird es zum Decoder mit konsekutive, nummerierten Zahlen im Gegensatz zum reinen DeMUX so zu sagen, der Eingabewert variieren kann, ist es immer nur eins und wird so zum Dekoda
Eine Rolle spielt bei diesem MIPS 32, dass sie den Ausgabe Operanten also dass sie das, was zum Beispiel in die ALU dann reingehen nicht abschalten können brauchen Sie nicht weil in die alu wird so oder sowas reingehen. Die Frage ist übernehmen Sie überhaupt den Wert von der alu des Macht eben der Befehl dekodierer und ebenso liegt am Registers Satz an beiden Quellen Operanten immer ein Wert an. Es ist halt die Frage, ob die übernommen wird aber sie schalten das nicht am Ausgang. Ab den Unterschied muss man begreifen.

Code: Select all

library ieee;
use ieee.std_logic_1164.all;
entity registerset2_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (4 downto 0);
    regsrc2: in std_logic_vector (4 downto 0);
    regdest: in std_logic_vector (4 downto 0);
    en: in std_logic;
);
end;

Letzter Beitrag so muss halt die Entity aussehen von einem 2 x 32 Beta Registers, Satz und jetzt brauchen wir Komponenten einmal den mux und einmal die des Register als Komponente und dann müssen wir die Komponenten sozusagen real werden lassen als zwei mux und dann nebenbei noch zwei Register, wobei das nichts miteinander zu tun haben. Die Register, die werden sich verdoppeln. Die Mux werden auch mehr durch die kaskadierung. Aber die mux sind ja in dem Fall nur zwei, weil sie zwei Quelloperanten haben

War jetzt so gesehen eben der Fehler drin aber das ist jetzt kein Problem. Ich bin jetzt schon bei der Architektur also das zu verbinden. Der Fehler war jetzt jetzt hatten wir 5 Bit für das Quellregister Auswahl und für die Ziel Register, das sind jetzt noch keine 5 Bit, weil das ist ja ein 2x32 und nicht 32x32 das kommt ja erst nachher die werden wir dann nachher weiter verbinden und deswegen haben wir bisher nur ein einziges Bild zur Auswahl. Das ist entweder null oder eins. Entweder das ist ein Register oder andere Register und deswegen ist es bisher nicht fünf bitte stimmte nicht

Code: Select all

library ieee;
use ieee.std_logic_1164.all;

entity registerset2_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic;
    regsrc2: in std_logic;
    regdest: in std_logic;
    en: in std_logic
);
end;

architecture behaviour of registerset2_32 is
    component reg32
    port (
        c: in std_logic;
        d: in std_logic_vector (31 downto 0);
        q: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal q1: std_logic_vector (31 downto 0);
    signal q2: std_logic_vector (31 downto 0);
    signal c1, c2: std_logic;
begin
    reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
    reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
    srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
    srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
    c1 <= en and regdest;
    c2 <= en and not regdest;
end;

Probieren, dazu Test zu schreiben können wir mal probieren wenn wir Lust dazu haben ein bisschen umständlich, dass wir sozusagen einmal in sein Register schreiben einmal in das andere und dann wählen wir aus welches Register wir meinen und dann gucken wir, ob der Wert darin gespeichert bleibt und wenn wir das andere Register auswählen, ob der Wert dann auch gespeichert bleibtgehe jetzt erst mal davon aus, dass das stimmt

Code: Select all

-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04

library ieee;
use ieee.std_logic_1164.all;

entity rslatch is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch is
begin
    q   <=  (r nor p);
    p   <=  (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch is
    component rslatch
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, d: std_logic;
begin
    rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
    d <= c and s;
    e <= c and r;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch is
    component clktriggeredrslatch
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatchtestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatchtestbench is
    component dlatch
    port (
        c: in std_logic;
        d: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff is
    component dlatch
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal e, a, b: std_logic;
begin
    d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
    d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
    a <= not c;
    b <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dfftestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dfftestbench is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dff PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity reg32 is
port (
    c: in std_logic;
    d: in std_logic_vector (31 downto 0);
    q: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of reg32 is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal p: std_logic_vector (31 downto 0);
begin
    gen_reg: FOR i in 31 downto 0 generate
        dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
        q(i) <= p (i);
    end generate;
end;

library ieee;
use ieee.std_logic_1164.all;


entity dffregtestbench is
port (
    q: inout std_logic_vector (31 downto 0)
);
end;

architecture behaviour of dffregtestbench is
    component reg32
    port (
        q: out std_logic_vector (31 downto 0);
        d: in std_logic_vector (31 downto 0);
        c: in std_logic
    );
    end component;
    signal d: std_logic_vector (31 downto 0);
    signal c: std_logic;
begin
    r32: reg32 PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1 is
port (
    c: out std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX32_2_1 is
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1testbench is
port (
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of MUX32_2_1testbench is
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal b: std_logic_vector (31 downto 0);
    signal a: std_logic_vector (31 downto 0);
    signal x: std_logic;
begin
    mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);

    a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
    b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
    x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset2_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic;
    regsrc2: in std_logic;
    regdest: in std_logic;
    en: in std_logic
);
end;

architecture behaviour of registerset2_32 is
    component reg32
    port (
        c: in std_logic;
        d: in std_logic_vector (31 downto 0);
        q: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal q1: std_logic_vector (31 downto 0);
    signal q2: std_logic_vector (31 downto 0);
    signal c1, c2: std_logic;
begin
    reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
    reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
    srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
    srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
    c1 <= en and regdest;
    c2 <= en and not regdest;
end;

Jetzt tue ich es einfach auf die Homepage und dann ist nicht mehr viel zu machen jetzt mache ich noch ein 4 x 32 Registers hat nämlich noch mal ne Komponente und da muss nicht mehr viel rein. Da muss noch eine Komponente von dem bisherigen Registers Satz rein und davon definieren wir jeweils zwei sozusagen existierende Einheiten also real existierende und dann gehört noch ein multiplexer dazu

Sieht so aus, als würde der Registers Satz. Ich hab ihn gerade einigermaßen getestet funktioniert. Ich gebe jetzt folgendes zu bedenken. Zunächst mal ist für alle Befehle die es gibt der Befehl Decoder eine wieder eigene Geschichte weil ich muss ja alle Befehle umsetzen. Es ist zwar relativ einfach gemacht aber trotzdem sind wir dann doch noch mal ein paar Sachen und ich würde gern schon wissen ob besser tut dann kann ich einen einzigen Befehl sozusagen umsetzen und zwar mit dem Registers Satz ich hab relativ schnellen Speicher gemacht, ob der jetzt 128 Byte hat oder ob der 1024 Byte hat ist ja egal. Unabhängig vom Speicher kann ich den Registers Satz benutzen für den Arithmetisch Befehl add ohne alle Befehle umgesetzt zu haben, kann ich dann den Prozessor schon mal testen. Sobald der Registers fertig ist, muss ich die alu komplett fertig machen und dann hab ich auch komplett fertig machen dann hab ich auch schon fast alles. Ich hab ja die multiplexer bereits
Das zweite ist ich gebe beim Registers Satz noch mal zu bedenken. Das Thema ist schon öfter aufgetaucht. Am Anfang sind die Werte im Registers Satz undefiniert. Problem ist, dass jedes Register im Registersatz erst ein Wert übernehmen muss sonst sind die Werte undefiniert. Das hatte ich beim ersten Versuchen so gemacht, dass ich ne Leitung in den Registers Satz eingebaut habe, die sozusagen alle auf null gesetzt hat. Das ist Unsinn das geht mit dem bisherigen. Ich hab's grad beim Testen festgestellt
Das ist beim Prozessor die Aufgabe RESET damit es stattfindet, gibt es die Aufgabe Reset, das ist ein eigener Prozess so, und das ist notwendig, weil sonst die Registerwerte undefiniert sind. Wenn die das aber sind, dann passiert folgendes in VHDL kann der Code nicht funktionieren weil die Register sind ja Eingabe und Ausgabe gleichzeitig. Dann pflanzt sich die fehlerhafte Ausgabe aber auf die Eingabe fort und die Werte bleiben undefiniert d.h. die Sache bleibt die ganze Zeit undefiniert beziehungsweise die Simulation bricht ab, weil wenn ich mit und definierten Werten arbeiten, bricht die Simulation ab, d.h. ich muss im ersten Schritt. Bei einem Reset muss ich erst alle Registern sozusagen den Wert null zu weisen.

Danke, wer sich wundert, dass es nicht so viele Befehle sind. Das sind schon viele. Aber warten sie haben Transfer Befehle, Register Speicher, Speicher Register, Register Register, Register Konstante, mathematisch add, sub, or, and und Verzweigungen, letzteres werden die meisten spannend finden ist aber schnell gemacht, <,=,> kleiner, gleich, größer, dazu müssen sie die Adresse im programmspeicher ändern, das geschieht mit einigen der vier mux

So, ich muss dir leider unter den Dusche wie jeder und kurz putzen ging nicht anders und jetzt werde ich gleich den 4 × 32 Registers Satz machen was passiert ist. Ich probier heut noch den MIPS 32 soweit fertig zu stellen, dass er zwei Befehle kann nämlich add und ldi ldi ist laden eines immediatisiere wert d.h. eines Direktwertes konstante das ist notwendig, weil eben die Konstante im Befehl steht und kein Register ist und keine Speicher einstelle. Und wenn ich das nicht mache, dann sind vielleicht alle Register gleich null dann bringt die Addition nicht weil 0 + 0 ist gleich null so, das andere Möglichkeit wäre den Befehl. Addi zu realisieren. Das ist der Befehl Addition mit Konstante statt einem Ziel, Registern und zwei quellregistern kann ich eine Konstante addieren das würde Sinn machen weil dann wird's nicht bei null bleiben

Post by **david** » Wed Dec 04, 2024 8:51 am

Ich glaube, ich hab's

Code: Select all

-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04

library ieee;
use ieee.std_logic_1164.all;

entity rslatch is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch is
begin
    q   <=  (r nor p);
    p   <=  (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch is
    component rslatch
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, d: std_logic;
begin
    rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
    d <= c and s;
    e <= c and r;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch is
    component clktriggeredrslatch
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatchtestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatchtestbench is
    component dlatch
    port (
        c: in std_logic;
        d: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff is
    component dlatch
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal e, a, b: std_logic;
begin
    d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
    d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
    a <= not c;
    b <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dfftestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dfftestbench is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dff PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity reg32 is
port (
    c: in std_logic;
    d: in std_logic_vector (31 downto 0);
    q: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of reg32 is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal p: std_logic_vector (31 downto 0);
begin
    gen_reg: FOR i in 31 downto 0 generate
        dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
        q(i) <= p (i);
    end generate;
end;

library ieee;
use ieee.std_logic_1164.all;


entity dffregtestbench is
port (
    q: inout std_logic_vector (31 downto 0)
);
end;

architecture behaviour of dffregtestbench is
    component reg32
    port (
        q: out std_logic_vector (31 downto 0);
        d: in std_logic_vector (31 downto 0);
        c: in std_logic
    );
    end component;
    signal d: std_logic_vector (31 downto 0);
    signal c: std_logic;
begin
    r32: reg32 PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1 is
port (
    c: out std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX32_2_1 is
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1testbench is
port (
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of MUX32_2_1testbench is
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal b: std_logic_vector (31 downto 0);
    signal a: std_logic_vector (31 downto 0);
    signal x: std_logic;
begin
    mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);

    a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
    b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
    x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset2_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic;
    regsrc2: in std_logic;
    regdest: in std_logic;
    en: in std_logic
);
end;

architecture behaviour of registerset2_32 is
    component reg32
    port (
        c: in std_logic;
        d: in std_logic_vector (31 downto 0);
        q: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal q1: std_logic_vector (31 downto 0);
    signal q2: std_logic_vector (31 downto 0);
    signal c1, c2: std_logic;
begin
    reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
    reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
    srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
    srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
    c1 <= en and not regdest;
    c2 <= en and regdest;
end;

library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset2_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset2_32testbench is
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic;
    signal    regsrc2: std_logic;
    signal    regdest: std_logic;
    signal    en: std_logic;

begin
    regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    regdest <= '0' after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
    regdest <= '0' after 0 ns;
    regsrc1 <= '0' after 0 ns;
    regsrc2 <= '0' after 0 ns;
end;

library ieee;
use ieee.std_logic_1164.all;


entity registerset4_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (1 downto 0);
    regsrc2: in std_logic_vector (1 downto 0);
    regdest: in std_logic_vector (1 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset4_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
    reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
    reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
    en2 <= regdest (1) and en;
    en1 <= not regdest (1) and en;
end;


library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset4_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset4_32testbench is
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic_vector (1 downto 0);
    signal    regsrc2: std_logic_vector (1 downto 0);
    signal    regdest: std_logic_vector (1 downto 0);
    signal    en: std_logic;

begin
    regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    regdest  <= ('0','0') after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
    regdest <= ('0','0') after 0 ns;
    regsrc1 <= ('0','0') after 0 ns;
    regsrc2 <= ('0','0') after 0 ns;
end;

Einen Test schreiben, ob das ob das überhaupt funktioniert mit vier Registern und wenn es mit vier Registern funktioniert, dann wird es ebenso mit acht Registern damit 16 und damit 32 Register funktionieren und dann müsste der Registers Satz fertig sein

Code: Select all

library ieee;
use ieee.std_logic_1164.all;

entity registerset2_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic;
    regsrc2: in std_logic;
    regdest: in std_logic;
    en: in std_logic
);
end;

architecture behaviour of registerset2_32 is
    component reg32
    port (
        c: in std_logic;
        d: in std_logic_vector (31 downto 0);
        q: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal q1: std_logic_vector (31 downto 0);
    signal q2: std_logic_vector (31 downto 0);
    signal c1, c2: std_logic;
begin
    reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
    reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
    srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
    srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
    c1 <= en and not regdest;
    c2 <= en and regdest;
end;

library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

-- ...

library ieee;
use ieee.std_logic_1164.all;


entity registerset4_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (1 downto 0);
    regsrc2: in std_logic_vector (1 downto 0);
    regdest: in std_logic_vector (1 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset4_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
    reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
    reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
    en2 <= regdest (1) and en;
    en1 <= not regdest (1) and en;
end;


library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset4_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset4_32testbench is
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic_vector (1 downto 0);
    signal    regsrc2: std_logic_vector (1 downto 0);
    signal    regdest: std_logic_vector (1 downto 0);
    signal    en: std_logic;

begin
    regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    regdest  <= ('0','0') after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
    regdest <= ('0','0') after 0 ns;
    regsrc1 <= ('0','0') after 0 ns;
    regsrc2 <= ('0','0') after 0 ns;
end;

und siehe da, es funktioniert!

jetzt kommt das auf die Homepage, dann mache ich den Test komplizierter, um eindeutige sicherheit zu haben, er geht fuer alle 4 Register. Ich mache den Test sehr ausgedehnt. Das ich je nach lesen und schreiben immer entsprechend schoen die Register habe. Danach mache ich ohne problem aus den 4 Registern 8, dann 16, dann 32, nach dem Schema wie gerade eben. Wenn das geschehen ist, dann mache ich die ALU, so, dass sie etwas hergibt. Ich mache 128 Byte RAM und den Festwertspeicher fuer das Programm laesst sich simpel fuellen. Ich muss nur noch die MUX verarbeiten wie im Blockschaltbild und dann ist nicht mehr viel zu tun, etwas mehr aufwand wird RESET, aber das laesst sich mit Zuweisung after '0' after 1 ns leicht erreichen

Ich mach kurz Pause ich denk das hat gut funktioniert. Jetzt kommt der super Test und die ganzen vier Register zu testen. Machen wir ein bisschen Pause und dann gucken wir mal

Das Register scheint zu funktionieren.

So, das Register scheint tatsaechlich gut zu funktionieren.

Der Registersatz scheint die Erwartungen zu erfuellen

Code: Select all

-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04

library ieee;
use ieee.std_logic_1164.all;

entity rslatch is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch is
begin
    q   <=  (r nor p);
    p   <=  (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch is
    component rslatch
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, d: std_logic;
begin
    rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
    d <= c and s;
    e <= c and r;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch is
    component clktriggeredrslatch
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatchtestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatchtestbench is
    component dlatch
    port (
        c: in std_logic;
        d: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff is
    component dlatch
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal e, a, b: std_logic;
begin
    d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
    d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
    a <= not c;
    b <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dfftestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dfftestbench is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dff PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity reg32 is
port (
    c: in std_logic;
    d: in std_logic_vector (31 downto 0);
    q: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of reg32 is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal p: std_logic_vector (31 downto 0);
begin
    gen_reg: FOR i in 31 downto 0 generate
        dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
        q(i) <= p (i);
    end generate;
end;

library ieee;
use ieee.std_logic_1164.all;


entity dffregtestbench is
port (
    q: inout std_logic_vector (31 downto 0)
);
end;

architecture behaviour of dffregtestbench is
    component reg32
    port (
        q: out std_logic_vector (31 downto 0);
        d: in std_logic_vector (31 downto 0);
        c: in std_logic
    );
    end component;
    signal d: std_logic_vector (31 downto 0);
    signal c: std_logic;
begin
    r32: reg32 PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1 is
port (
    c: out std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX32_2_1 is
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1testbench is
port (
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of MUX32_2_1testbench is
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal b: std_logic_vector (31 downto 0);
    signal a: std_logic_vector (31 downto 0);
    signal x: std_logic;
begin
    mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);

    a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
    b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
    x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset2_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic;
    regsrc2: in std_logic;
    regdest: in std_logic;
    en: in std_logic
);
end;

architecture behaviour of registerset2_32 is
    component reg32
    port (
        c: in std_logic;
        d: in std_logic_vector (31 downto 0);
        q: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal q1: std_logic_vector (31 downto 0);
    signal q2: std_logic_vector (31 downto 0);
    signal c1, c2: std_logic;
begin
    reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
    reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
    srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
    srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
    c1 <= en and not regdest;
    c2 <= en and regdest;
end;

library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset2_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset2_32testbench is
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic;
    signal    regsrc2: std_logic;
    signal    regdest: std_logic;
    signal    en: std_logic;

begin
    regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    regdest <= '0' after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
    regdest <= '0' after 0 ns;
    regsrc1 <= '0' after 0 ns;
    regsrc2 <= '0' after 0 ns;
end;

library ieee;
use ieee.std_logic_1164.all;


entity registerset4_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (1 downto 0);
    regsrc2: in std_logic_vector (1 downto 0);
    regdest: in std_logic_vector (1 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset4_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
    reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
    reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
    en2 <= regdest (1) and en;
    en1 <= not regdest (1) and en;
end;


library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset4_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset4_32testbench is
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic_vector (1 downto 0);
    signal    regsrc2: std_logic_vector (1 downto 0);
    signal    regdest: std_logic_vector (1 downto 0);
    signal    en: std_logic;

begin
    regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    -- regdest  <= ('0','0') after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
    regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
    regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
    regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;


library ieee;
use ieee.std_logic_1164.all;


entity registerset8_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (2 downto 0);
    regsrc2: in std_logic_vector (2 downto 0);
    regdest: in std_logic_vector (2 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset8_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
    reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
    reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
    en2 <= regdest (2) and en;
    en1 <= not regdest (2) and en;
end;


library ieee;
use ieee.std_logic_1164.all;

entity registerset16_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (3 downto 0);
    regsrc2: in std_logic_vector (3 downto 0);
    regdest: in std_logic_vector (3 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset16_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset8_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (2 downto 0);
        regsrc2: in std_logic_vector (2 downto 0);
        regdest: in std_logic_vector (2 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
    reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
    reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
    en2 <= regdest (3) and en;
    en1 <= not regdest (3) and en;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset32_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (4 downto 0);
    regsrc2: in std_logic_vector (4 downto 0);
    regdest: in std_logic_vector (4 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset32_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset16_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (3 downto 0);
        regsrc2: in std_logic_vector (3 downto 0);
        regdest: in std_logic_vector (3 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
    reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
    reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
    en2 <= regdest (4) and en;
    en1 <= not regdest (4) and en;
end;

dann geht es mit 16 auch und 32 auch und betrachte, das erst mal als erledigt, wichtig ist, dass wir jetzt einen Vektor spalten
Wenn wir zum beispiel mit 32 Bit haben und in Lower und Higher aufteilen wollen, dann brauchen wir

Code: Select all

signal dword32: std_logic_vector (31 downto 0);
signal word16low: std_logic_vector (15 downto 0);
signal word16high: std_logic_vector (15 downto 0);
word16low <= dword32  (15 downto 0);

Post by **david** » Wed Dec 04, 2024 10:57 am

Code: Select all

-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04

library ieee;
use ieee.std_logic_1164.all;

entity rslatch is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch is
begin
    q   <=  (r nor p);
    p   <=  (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch is
    component rslatch
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, d: std_logic;
begin
    rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
    d <= c and s;
    e <= c and r;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch is
    component clktriggeredrslatch
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatchtestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatchtestbench is
    component dlatch
    port (
        c: in std_logic;
        d: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff is
    component dlatch
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal e, a, b: std_logic;
begin
    d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
    d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
    a <= not c;
    b <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dfftestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dfftestbench is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dff PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity reg32 is
port (
    c: in std_logic;
    d: in std_logic_vector (31 downto 0);
    q: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of reg32 is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal p: std_logic_vector (31 downto 0);
begin
    gen_reg: FOR i in 31 downto 0 generate
        dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
        q(i) <= p (i);
    end generate;
end;

library ieee;
use ieee.std_logic_1164.all;


entity dffregtestbench is
port (
    q: inout std_logic_vector (31 downto 0)
);
end;

architecture behaviour of dffregtestbench is
    component reg32
    port (
        q: out std_logic_vector (31 downto 0);
        d: in std_logic_vector (31 downto 0);
        c: in std_logic
    );
    end component;
    signal d: std_logic_vector (31 downto 0);
    signal c: std_logic;
begin
    r32: reg32 PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1 is
port (
    c: out std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX32_2_1 is
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1testbench is
port (
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of MUX32_2_1testbench is
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal b: std_logic_vector (31 downto 0);
    signal a: std_logic_vector (31 downto 0);
    signal x: std_logic;
begin
    mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);

    a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
    b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
    x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset2_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic;
    regsrc2: in std_logic;
    regdest: in std_logic;
    en: in std_logic
);
end;

architecture behaviour of registerset2_32 is
    component reg32
    port (
        c: in std_logic;
        d: in std_logic_vector (31 downto 0);
        q: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal q1: std_logic_vector (31 downto 0);
    signal q2: std_logic_vector (31 downto 0);
    signal c1, c2: std_logic;
begin
    reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
    reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
    srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
    srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
    c1 <= en and not regdest;
    c2 <= en and regdest;
end;

library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset2_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset2_32testbench is
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic;
    signal    regsrc2: std_logic;
    signal    regdest: std_logic;
    signal    en: std_logic;

begin
    regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    regdest <= '0' after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
    regdest <= '0' after 0 ns;
    regsrc1 <= '0' after 0 ns;
    regsrc2 <= '0' after 0 ns;
end;

library ieee;
use ieee.std_logic_1164.all;


entity registerset4_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (1 downto 0);
    regsrc2: in std_logic_vector (1 downto 0);
    regdest: in std_logic_vector (1 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset4_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
    reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
    reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
    en2 <= regdest (1) and en;
    en1 <= not regdest (1) and en;
end;


library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset4_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset4_32testbench is
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic_vector (1 downto 0);
    signal    regsrc2: std_logic_vector (1 downto 0);
    signal    regdest: std_logic_vector (1 downto 0);
    signal    en: std_logic;

begin
    regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    -- regdest  <= ('0','0') after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
    regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
    regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
    regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;


library ieee;
use ieee.std_logic_1164.all;


entity registerset8_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (2 downto 0);
    regsrc2: in std_logic_vector (2 downto 0);
    regdest: in std_logic_vector (2 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset8_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
    reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
    reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
    en2 <= regdest (2) and en;
    en1 <= not regdest (2) and en;
end;


library ieee;
use ieee.std_logic_1164.all;

entity registerset16_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (3 downto 0);
    regsrc2: in std_logic_vector (3 downto 0);
    regdest: in std_logic_vector (3 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset16_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset8_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (2 downto 0);
        regsrc2: in std_logic_vector (2 downto 0);
        regdest: in std_logic_vector (2 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
    reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
    reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
    en2 <= regdest (3) and en;
    en1 <= not regdest (3) and en;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset32_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (4 downto 0);
    regsrc2: in std_logic_vector (4 downto 0);
    regdest: in std_logic_vector (4 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset32_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset16_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (3 downto 0);
        regsrc2: in std_logic_vector (3 downto 0);
        regdest: in std_logic_vector (3 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
    reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
    reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
    en2 <= regdest (4) and en;
    en1 <= not regdest (4) and en;
end;

Post by **david** » Wed Dec 04, 2024 2:28 pm

Hier noch mal

Code: Select all

-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04

library ieee;
use ieee.std_logic_1164.all;

entity rslatch is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch is
begin
    q   <=  (r nor p);
    p   <=  (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch is
    component rslatch
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, d: std_logic;
begin
    rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
    d <= c and s;
    e <= c and r;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch is
    component clktriggeredrslatch
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatchtestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatchtestbench is
    component dlatch
    port (
        c: in std_logic;
        d: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff is
    component dlatch
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal e, a, b: std_logic;
begin
    d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
    d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
    a <= not c;
    b <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dfftestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dfftestbench is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dff PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity reg32 is
port (
    c: in std_logic;
    d: in std_logic_vector (31 downto 0);
    q: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of reg32 is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal p: std_logic_vector (31 downto 0);
begin
    gen_reg: FOR i in 31 downto 0 generate
        dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
        q(i) <= p (i);
    end generate;
end;

library ieee;
use ieee.std_logic_1164.all;


entity dffregtestbench is
port (
    q: inout std_logic_vector (31 downto 0)
);
end;

architecture behaviour of dffregtestbench is
    component reg32
    port (
        q: out std_logic_vector (31 downto 0);
        d: in std_logic_vector (31 downto 0);
        c: in std_logic
    );
    end component;
    signal d: std_logic_vector (31 downto 0);
    signal c: std_logic;
begin
    r32: reg32 PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1 is
port (
    c: out std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX32_2_1 is
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1testbench is
port (
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of MUX32_2_1testbench is
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal b: std_logic_vector (31 downto 0);
    signal a: std_logic_vector (31 downto 0);
    signal x: std_logic;
begin
    mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);

    a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
    b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
    x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset2_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic;
    regsrc2: in std_logic;
    regdest: in std_logic;
    en: in std_logic
);
end;

architecture behaviour of registerset2_32 is
    component reg32
    port (
        c: in std_logic;
        d: in std_logic_vector (31 downto 0);
        q: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal q1: std_logic_vector (31 downto 0);
    signal q2: std_logic_vector (31 downto 0);
    signal c1, c2: std_logic;
begin
    reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
    reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
    srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
    srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
    c1 <= en and not regdest;
    c2 <= en and regdest;
end;

library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset2_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset2_32testbench is
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic;
    signal    regsrc2: std_logic;
    signal    regdest: std_logic;
    signal    en: std_logic;

begin
    regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    regdest <= '0' after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
    regdest <= '0' after 0 ns;
    regsrc1 <= '0' after 0 ns;
    regsrc2 <= '0' after 0 ns;
end;

library ieee;
use ieee.std_logic_1164.all;


entity registerset4_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (1 downto 0);
    regsrc2: in std_logic_vector (1 downto 0);
    regdest: in std_logic_vector (1 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset4_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
    reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
    reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
    en2 <= regdest (1) and en;
    en1 <= not regdest (1) and en;
end;


library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset4_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset4_32testbench is
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic_vector (1 downto 0);
    signal    regsrc2: std_logic_vector (1 downto 0);
    signal    regdest: std_logic_vector (1 downto 0);
    signal    en: std_logic;

begin
    regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    -- regdest  <= ('0','0') after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
    regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
    regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
    regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;


library ieee;
use ieee.std_logic_1164.all;


entity registerset8_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (2 downto 0);
    regsrc2: in std_logic_vector (2 downto 0);
    regdest: in std_logic_vector (2 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset8_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
    reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
    reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
    en2 <= regdest (2) and en;
    en1 <= not regdest (2) and en;
end;


library ieee;
use ieee.std_logic_1164.all;

entity registerset16_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (3 downto 0);
    regsrc2: in std_logic_vector (3 downto 0);
    regdest: in std_logic_vector (3 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset16_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset8_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (2 downto 0);
        regsrc2: in std_logic_vector (2 downto 0);
        regdest: in std_logic_vector (2 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
    reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
    reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
    en2 <= regdest (3) and en;
    en1 <= not regdest (3) and en;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset32_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (4 downto 0);
    regsrc2: in std_logic_vector (4 downto 0);
    regdest: in std_logic_vector (4 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset32_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset16_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (3 downto 0);
        regsrc2: in std_logic_vector (3 downto 0);
        regdest: in std_logic_vector (3 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
    reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
    reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
    en2 <= regdest (4) and en;
    en1 <= not regdest (4) and en;
end;

Post by **david** » Wed Dec 04, 2024 2:31 pm

jetzt tue ich das auf die homepage. Wenn das geschehen ist, dann pause, dann mache die ALU komplett, mit steuerwort und mit den 5 Funktionen. Dann - wird alles zusammen geschaltet, was da ist.

Mach jetzt die ALU aus dem subtrahier und dem addier, un musst du noch die Logik einbauen

Code: Select all

-- jetzt kann man das so machen

library ieee;
use ieee.std_logic_1164.all;

entity ALU is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    s: in std_logic_vector (2 downto 0);
    t: out std_logic;
    null: out std_logic
);
end;

architecture behaviour of ALU is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    component and32
    port (

    );
    end component;

begin

end;

Code: Select all

library ieee;
use ieee.std_logic_1164.all;

entity or32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
);
end;

architecture behaviour of or32 is
begin
    genor32: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= b (i) or a (i);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity and32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
);
end;

architecture behaviour of and32 is
begin
    genand32: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= b (i) and a (i);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity ALU is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    s: in std_logic_vector (2 downto 0);
    t: out std_logic;
    null: out std_logic
);
end;

architecture behaviour of ALU is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    component and32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
    );
    end component;
    component or32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
    );
    end component;
begin

end;

Und noch weiter

Code: Select all

library ieee;
use ieee.std_logic_1164.all;

entity or32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
);
end;

architecture behaviour of or32 is
begin
    genor32: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= b (i) or a (i);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity and32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
);
end;

architecture behaviour of and32 is
begin
    genand32: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= b (i) and a (i);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1 is
port (
    c: out std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX32_2_1 is
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity ALU is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    s: in std_logic_vector (2 downto 0);
    t: out std_logic;
    null: out std_logic
);
end;

architecture behaviour of ALU is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    component and32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
    );
    end component;
    component or32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
    );
    end component;
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
begin
    -- 010 add
    -- 110 sub
    -- 000 and
    -- 001 or
    -- 111 slt set less than
    mux1: MUX32_2_1 PORT MAP (a=>cadd);
    mux2: MUX32_2_1 PORT MAP ();
    mux3: MUX32_2_1 PORT MAP ();
    add1: add1 PORT MAP (a=>a, b=>b, s=>sadd, t=>globaltflag, c=>cadd);
    sub1: sub1 PORT MAP (a=>a, b=>b, t=>globaltflag, c=>csub);
    and1: and1 PORT MAP (a=>a, b=>b, c=>cand);
    or1: or1 PORT MAP (a=>a, b=>b, c=>cor);
end;

Es hat wohl funktioniert

Code: Select all

-- es scheint funktioniert zu haben

library ieee;
use ieee.std_logic_1164.all;

entity ALU is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    s: in std_logic_vector (2 downto 0);
    t: out std_logic;
    nul: out std_logic;
    globalcarryflag: out std_logic
);
end;

architecture behaviour of ALU is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    component and32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component or32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal z4, z3, z2, z1: std_logic;
    signal x3, x2, x1: std_logic;
    signal csub: std_logic_vector (31 downto 0);
    signal cor: std_logic_vector (31 downto 0);
    signal cmux1: std_logic_vector (31 downto 0);
    signal cmux2: std_logic_vector (31 downto 0);
    signal cadd: std_logic_vector (31 downto 0);
    signal cand:  std_logic_vector (31 downto 0);
    signal sadd: std_logic;
begin
    -- 010 add
    -- 110 sub
    -- 000 and
    -- 001 or
    -- 111 slt set less than
    mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
    mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
    mux3: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>c, x=>x3);
    add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
    sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
    and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
    or1: or32 PORT MAP (a=>a, b=>b, c=>cor);

    z1 <= (not s (2) and s (1) and not s (0));
    z2 <= (s(2) and s(1) and not s(0));
    z3 <= (not s (2) and not s (1) and not s (0));
    z4 <= (not s (2) and not s (1) and s (0));

    --
    -- z4  z3  z2  z1       x3  x2  x1
    -- 0   0   0   1        0   x   0
    -- 0   0   1   0        0   x   1
    -- 0   1   0   0        1   1   x
    -- 1   0   0   0        1   0   x

    -- x3 <= z3 or z4
    -- x2 <= z3
    -- x1 <= z2

    x3 <= z3 or z4;
    x2 <= z3;
    x1 <= z2;
    sadd <= '0';
end;

Post by **david** » Wed Dec 04, 2024 2:32 pm

Code: Select all

-- (C) David Vajda
-- D-FF/32 x 32 Bit Register set MIPS32/2 Src, 1 Dest
-- 2024-11-28/2024-12-04

library ieee;
use ieee.std_logic_1164.all;

entity rslatch is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch is
begin
    q   <=  (r nor p);
    p   <=  (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch is
    component rslatch
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, d: std_logic;
begin
    rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
    d <= c and s;
    e <= c and r;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch is
    component clktriggeredrslatch
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatchtestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatchtestbench is
    component dlatch
    port (
        c: in std_logic;
        d: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff is
    component dlatch
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal e, a, b: std_logic;
begin
    d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
    d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
    a <= not c;
    b <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dfftestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dfftestbench is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dff PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity reg32 is
port (
    c: in std_logic;
    d: in std_logic_vector (31 downto 0);
    q: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of reg32 is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal p: std_logic_vector (31 downto 0);
begin
    gen_reg: FOR i in 31 downto 0 generate
        dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
        q(i) <= p (i);
    end generate;
end;

library ieee;
use ieee.std_logic_1164.all;


entity dffregtestbench is
port (
    q: inout std_logic_vector (31 downto 0)
);
end;

architecture behaviour of dffregtestbench is
    component reg32
    port (
        q: out std_logic_vector (31 downto 0);
        d: in std_logic_vector (31 downto 0);
        c: in std_logic
    );
    end component;
    signal d: std_logic_vector (31 downto 0);
    signal c: std_logic;
begin
    r32: reg32 PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1 is
port (
    c: out std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX32_2_1 is
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1testbench is
port (
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of MUX32_2_1testbench is
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal b: std_logic_vector (31 downto 0);
    signal a: std_logic_vector (31 downto 0);
    signal x: std_logic;
begin
    mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);

    a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
    b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
    x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset2_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic;
    regsrc2: in std_logic;
    regdest: in std_logic;
    en: in std_logic
);
end;

architecture behaviour of registerset2_32 is
    component reg32
    port (
        c: in std_logic;
        d: in std_logic_vector (31 downto 0);
        q: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal q1: std_logic_vector (31 downto 0);
    signal q2: std_logic_vector (31 downto 0);
    signal c1, c2: std_logic;
begin
    reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
    reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
    srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
    srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
    c1 <= en and not regdest;
    c2 <= en and regdest;
end;

library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset2_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset2_32testbench is
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic;
    signal    regsrc2: std_logic;
    signal    regdest: std_logic;
    signal    en: std_logic;

begin
    regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    regdest <= '0' after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
    regdest <= '0' after 0 ns;
    regsrc1 <= '0' after 0 ns;
    regsrc2 <= '0' after 0 ns;
end;

library ieee;
use ieee.std_logic_1164.all;


entity registerset4_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (1 downto 0);
    regsrc2: in std_logic_vector (1 downto 0);
    regdest: in std_logic_vector (1 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset4_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
    reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
    reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
    en2 <= regdest (1) and en;
    en1 <= not regdest (1) and en;
end;


library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset4_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset4_32testbench is
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic_vector (1 downto 0);
    signal    regsrc2: std_logic_vector (1 downto 0);
    signal    regdest: std_logic_vector (1 downto 0);
    signal    en: std_logic;

begin
    regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    -- regdest  <= ('0','0') after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
    regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
    regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
    regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;


library ieee;
use ieee.std_logic_1164.all;


entity registerset8_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (2 downto 0);
    regsrc2: in std_logic_vector (2 downto 0);
    regdest: in std_logic_vector (2 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset8_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
    reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
    reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
    en2 <= regdest (2) and en;
    en1 <= not regdest (2) and en;
end;


library ieee;
use ieee.std_logic_1164.all;

entity registerset16_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (3 downto 0);
    regsrc2: in std_logic_vector (3 downto 0);
    regdest: in std_logic_vector (3 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset16_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset8_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (2 downto 0);
        regsrc2: in std_logic_vector (2 downto 0);
        regdest: in std_logic_vector (2 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
    reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
    reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
    en2 <= regdest (3) and en;
    en1 <= not regdest (3) and en;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset32_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (4 downto 0);
    regsrc2: in std_logic_vector (4 downto 0);
    regdest: in std_logic_vector (4 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset32_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset16_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (3 downto 0);
        regsrc2: in std_logic_vector (3 downto 0);
        regdest: in std_logic_vector (3 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
    reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
    reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
    en2 <= regdest (4) and en;
    en1 <= not regdest (4) and en;
end;

Post by **david** » Wed Dec 04, 2024 2:33 pm

jetzt sind wir fast am ziel - unser befehlszaehler, ist ein 32 Bit Register, zu dem wir einen addierer nehmen, der den Wert 4 Addiert. Unsere Beiden Speicher, Heap - Daten - Harvard - und statisch programm - sind - dasselbe wie ein Registersatz, allerdings nur ein Quelloperand, so zu sagen, da machen wir aber nicht 32, sondern 128, dann die ALU ist da - registersatz auch, 4 MUX, die sind da, noch ein addierer, 1 2 Bit Shifter, das duerfte kein problem sein, Vorzeichenerweiterungseinheit, da tue ich mich ein bischen schwer, dann der Funktionsdekodierer und Befehlsdekodierer, die zunaechst zwei Befehle verstehen, dann fertig. Der Rest der Befehle folgt.

Also ich mach jetzt folgendes da bleibt nicht mehr viel zu tun. Es muss jetzt erst mal auf die Homepage. Das ist das wichtigste, dass es auf der Homepage ist und ich hab schon die mips 32 vhdl Datei erstellt die existiert jetzt soweit. Es muss jetzt auf die Homepage und sobald es da ist kann ich anfangen die Sache zusammenzusetzen das ganze Ding und dabei hab ich noch keine Vorzeichenerwartung Einheit und ich glaub das wird dann kein Problem sein weil wie gesagt, ich werde gleich nicht alle Befehle implementieren es wird nur ein Addition, Befehl geben und ein Lade Befehl für Direktwerte also konstanten und dabei wird die Vorzeichenerweiterung Einheit, die bei Verzweigungen eine Rolle spielt keine Rolle spielen deswegen werde ich sie nicht außen vor lassen. Aber denken Sie nach, das sind ja alles Komponenten. Die werden irgendwo anders definiert. Wenn die sowieso nicht benutzt wird dann können Sie das selbe Signal rausschicken, was sie einfach wieder rein schicken Wenn Sie das nicht benutzen, ist es relativ egal und das können Sie nachher von Ihnen her erweitern. Ganz einfach erst muss es auf die Homepage schon gleich mache ich das dann fertig. Es wird noch heute Abend fertig sein der MIPS 32 mit zwei Befehlen.

Post by **david** » Wed Dec 04, 2024 10:57 pm

Entweder macht Übersetzer manchmal viel seltsame Fehler da sind grammatische Sachen drin die fallen mir aber nicht auf wenn ich das hier diktiere ist mir aber gerade aufgefallen Jetzt ist mir gerade aufgefallen, da stand totaler Schwachsinn. na gut oder? Man muss ja auch aufpassen auf Facebook da können ja auch das können ja selbst Polizisten sein, mal Leute ihren Account freischalten . Keine Sorge, meine Homepage ist nicht zu hacken das ist halt der Unterschied. Ich glaube auch, dass Facebook nicht zu hacken ist, letztenendes aber, dass man sich politisch also rechtsmäßig den Zugangscode legitimen verschaffen kann und wer weiß wer da was dann rein schreibt für ihr Zeug. Das ist bei meiner Homepage nicht möglich die Homepage wiederum Mag ja unsicherer klingen als Facebook aber sie kommen da einfach nicht rein sonst muss man einfach sagen Sie kommen in meine Homepage nicht rein, weil es ist mein Computer. Das ist halt so. Manchmal sind auch die Vorschläge vom Diktier Dingsbums sehr seltsam, muss ich sagen
Letztenendes muss ich allerdings sagen ist mir die Art und Weise wie ich etwas diktiere scheißegal Sie müssen wissen mir geht's um das Schreiben der VHDL Codes und ich sag mal so mir ist es gerade recht wenn's unsauber rauskommen. Ich hab schon Texte vom Chinesen in Technik gelesen die waren genauso schräg ungefähr so schräg und sie waren lesbar von der technischen Seite her und wir brauchen sie nicht. Ich bin übrigens kein chinesischer Hacker. Ich bin David Vajda

Von der technischen Seite her ist es sogar gut, wenn der Diktier ein bisschen Scheiße macht. Das ist halt Technik und diktiere. So sehe ich das, dass man dann erkennt, dass es Technik und diktiere und nichts anderes weil eigentlich mag ich keine Polemik. Ich weiß nur darauf hin, wie wenig mir das alles gefällt Ansonsten kann der Text ruhig technisch sein und wenn es technisch ist, dann ist es genau richtig weil mir geht's um die Sache vhdl und nicht das andere

Sag ich mal so zum Beispiel Atomwaffentest weil meine Gatter haben mit Atomwaffen Nix zu tun trotzdem wenn sie das mal anschauen als die Amerikaner angefangen haben. Die waren schon längst in der Lage in Atomwaffentest zu machen. So ging's mir mit den MIPS 32 auch trotzdem hab ich gesagt, wir warten wir warten. Wir warten das zweite ist es gibt die Übung 10.000 mal also die noch nicht voll reife Übung einfach um das zu machen und dann steht diesmal Datum und Uhrzeit drauf so wie bei mir und dann der letzte Witz. Ja wenn das halt stattfindet, dann müssen sie halt alles aufnehmen diktieren diktieren diktieren was passiert ob das jetzt 100 % ins Deutschunterricht reinpasst. Vor voller Grammatik ist es egal verstehen tut's von der technischen Seite hinterher jeder so auf die Art und Weise schon dann haben sind sie glücklich, wenn sie sie protokolliert Habenund so kam es halt drüber und das ist eigentlich sogar ne ehrliche Aufnahme im Gegensatz zu anderen

Code: Select all

-- (C) David Vajda
-- MIPS32 - minimal
-- 2024-12-04

library ieee;
use ieee.std_logic_1164.all;

entity rslatch is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch is
begin
    q   <=  (r nor p);
    p   <=  (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch is
    component rslatch
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, d: std_logic;
begin
    rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
    d <= c and s;
    e <= c and r;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch is
    component clktriggeredrslatch
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatchtestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatchtestbench is
    component dlatch
    port (
        c: in std_logic;
        d: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff is
    component dlatch
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal e, a, b: std_logic;
begin
    d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
    d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
    a <= not c;
    b <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dfftestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dfftestbench is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dff PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity reg32 is
port (
    c: in std_logic;
    d: in std_logic_vector (31 downto 0);
    q: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of reg32 is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal p: std_logic_vector (31 downto 0);
begin
    gen_reg: FOR i in 31 downto 0 generate
        dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
        q(i) <= p (i);
    end generate;
end;

library ieee;
use ieee.std_logic_1164.all;


entity dffregtestbench is
port (
    q: inout std_logic_vector (31 downto 0)
);
end;

architecture behaviour of dffregtestbench is
    component reg32
    port (
        q: out std_logic_vector (31 downto 0);
        d: in std_logic_vector (31 downto 0);
        c: in std_logic
    );
    end component;
    signal d: std_logic_vector (31 downto 0);
    signal c: std_logic;
begin
    r32: reg32 PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1 is
port (
    c: out std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX32_2_1 is
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX5_2_1 is
port (
    c: out std_logic_vector (4 downto 0);
    b: in std_logic_vector (4 downto 0);
    a: in std_logic_vector (4 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX5_2_1 is
begin
    MUX_generate: FOR i IN 4 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1testbench is
port (
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of MUX32_2_1testbench is
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal b: std_logic_vector (31 downto 0);
    signal a: std_logic_vector (31 downto 0);
    signal x: std_logic;
begin
    mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);

    a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
    b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
    x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset2_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic;
    regsrc2: in std_logic;
    regdest: in std_logic;
    en: in std_logic
);
end;

architecture behaviour of registerset2_32 is
    component reg32
    port (
        c: in std_logic;
        d: in std_logic_vector (31 downto 0);
        q: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal q1: std_logic_vector (31 downto 0);
    signal q2: std_logic_vector (31 downto 0);
    signal c1, c2: std_logic;
begin
    reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
    reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
    srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
    srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
    c1 <= en and not regdest;
    c2 <= en and regdest;
end;

library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset2_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset2_32testbench is
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic;
    signal    regsrc2: std_logic;
    signal    regdest: std_logic;
    signal    en: std_logic;

begin
    regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    regdest <= '0' after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
    regdest <= '0' after 0 ns;
    regsrc1 <= '0' after 0 ns;
    regsrc2 <= '0' after 0 ns;
end;

library ieee;
use ieee.std_logic_1164.all;


entity registerset4_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (1 downto 0);
    regsrc2: in std_logic_vector (1 downto 0);
    regdest: in std_logic_vector (1 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset4_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
    reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
    reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
    en2 <= regdest (1) and en;
    en1 <= not regdest (1) and en;
end;


library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset4_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset4_32testbench is
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic_vector (1 downto 0);
    signal    regsrc2: std_logic_vector (1 downto 0);
    signal    regdest: std_logic_vector (1 downto 0);
    signal    en: std_logic;

begin
    regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    -- regdest  <= ('0','0') after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
    regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
    regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
    regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;


library ieee;
use ieee.std_logic_1164.all;


entity registerset8_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (2 downto 0);
    regsrc2: in std_logic_vector (2 downto 0);
    regdest: in std_logic_vector (2 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset8_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
    reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
    reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
    en2 <= regdest (2) and en;
    en1 <= not regdest (2) and en;
end;


library ieee;
use ieee.std_logic_1164.all;

entity registerset16_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (3 downto 0);
    regsrc2: in std_logic_vector (3 downto 0);
    regdest: in std_logic_vector (3 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset16_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset8_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (2 downto 0);
        regsrc2: in std_logic_vector (2 downto 0);
        regdest: in std_logic_vector (2 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
    reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
    reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
    en2 <= regdest (3) and en;
    en1 <= not regdest (3) and en;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset32_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (4 downto 0);
    regsrc2: in std_logic_vector (4 downto 0);
    regdest: in std_logic_vector (4 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset32_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset16_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (3 downto 0);
        regsrc2: in std_logic_vector (3 downto 0);
        regdest: in std_logic_vector (3 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
    reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
    reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
    en2 <= regdest (4) and en;
    en1 <= not regdest (4) and en;
end;

-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02

library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
port (
    a: in std_logic;
    b: in std_logic;
    c: out std_logic;
    s: in std_logic;
    t: out std_logic
);
end;

architecture behaviour of fulladder is
begin
    c <= a xor b xor s;
    t <= (a and b) or ((a or b) and s);
end;

library ieee;
use ieee.std_logic_1164.all;

entity ripplecarrychainadder32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    s: in std_logic;
    t: out std_logic
);
end;

architecture behaviour of ripplecarrychainadder32 is
    component fulladder
    port (
        a: in std_logic;
        b: in std_logic;
        c: out std_logic;
        s: in std_logic;
        t: out std_logic
    );
    end component;
    signal x: std_logic_vector (32 downto 0);
begin
        fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
            fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
        END GENERATE;
        t <= x (32) ;
        x (0) <= s;
    --fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
    --fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
    --fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
    --fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;

library ieee;
use ieee.std_logic_1164.all;

entity ripplecarrychainadder32testbench is
port (
    c: out std_logic_vector (31 downto 0);
    t: out std_logic
);
end;


architecture behaviour of ripplecarrychainadder32testbench is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    signal a: std_logic_vector (31 downto 0);
    signal b: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    rplcadd: ripplecarrychainadder32 PORT MAP (c=>c, b=>b, a=>a, s=>s, t=>t);
    -- 19219 + 14823 = 34042
    -- 0b100101100010011 + 0b11100111100111 = 0b1000010011111010
    a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;

    b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
    s <= '0';
end;

library ieee;
use ieee.std_logic_1164.all;

entity com32 is
port (
    x: in std_logic_vector (31 downto 0);
    y: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of com32 is
begin
        com_connect: FOR i IN 31 DOWNTO 0 GENERATE
                y (i) <= not x (i);
        END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity neg32 is
port (
    b: out std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    t: out std_logic
);
end;

architecture behaviour of neg32 is
    component com32
    port (
        x: in std_logic_vector (31 downto 0);
        y: out std_logic_vector (31 downto 0)
    );
    end component;

    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    signal c: std_logic_vector (31 downto 0);
    signal d: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    neg32_generate_1: FOR i IN 31 DOWNTO 0 GENERATE
        d (i) <= '0';
    END GENERATE;
    s <= '1';
    com: com32 PORT MAP (x=>a, y=>c);
    add: ripplecarrychainadder32 PORT MAP (b=>d, a=>c, s=>s, t=>t, c=>b);
end;

library ieee;
use ieee.std_logic_1164.all;

entity sub32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    t: out std_logic
);
end;

architecture behaviour of sub32 is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component neg32
    port (
        b: out std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    signal x: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    neg: neg32 PORT MAP (a=>a, b=>x);
    add: ripplecarrychainadder32 PORT MAP (b=>b, a=>x, c=>c, s=>s, t=>t);
    s <= '0';
end;

library ieee;
use ieee.std_logic_1164.all;

entity sub32testbench is
port (
    c: out std_logic_vector (31 downto 0);
    t: out std_logic
);
end;


architecture behaviour of sub32testbench is
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    signal a: std_logic_vector (31 downto 0);
    signal b: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    sub: sub32 PORT MAP (a=>a, b=>b, c=>c, t=>t);

    a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
    b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns,  ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
    s <= '0' after 0 ns, '1' after 10 ns;
    -- 19219 - 14823 =
end;

library ieee;
use ieee.std_logic_1164.all;

entity or32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of or32 is
begin
    genor32: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= b (i) or a (i);
    END GENERATE;
end;


library ieee;
use ieee.std_logic_1164.all;

entity and32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of and32 is
begin
    genand32: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= b (i) and a (i);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;


    entity sram is
    port (
        en: in std_logic;
        addrs: in std_logic_vector (31 downto 0);
        writedata: in std_logic_vector (31 downto 0);
        readdata: out std_logic_vector (31 downto 0)
    );
    end;

    architecture behaviour of sram is
    begin
        readdata <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
    end;


library ieee;
use ieee.std_logic_1164.all;


    entity prom is
    port (
        addrs: in std_logic_vector (31 downto 0);
        readdata: out std_logic_vector (31 downto 0)
    );
    end;

    architecture behaviour of prom is
    begin

    end;


library ieee;
use ieee.std_logic_1164.all;

entity ALU is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    s: in std_logic_vector (2 downto 0);
    t: out std_logic;
    nul: inout std_logic;
    globalcarryflag: out std_logic
);
end;

architecture behaviour of ALU is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    component and32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component or32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal z4, z3, z2, z1: std_logic;
    signal x3, x2, x1: std_logic;
    signal csub: std_logic_vector (31 downto 0);
    signal cor: std_logic_vector (31 downto 0);
    signal cmux1: std_logic_vector (31 downto 0);
    signal cmux2: std_logic_vector (31 downto 0);
    signal cadd: std_logic_vector (31 downto 0);
    signal cand:  std_logic_vector (31 downto 0);
    signal sadd: std_logic;
    signal d: std_logic_vector (31 downto 0);
begin
    -- 010 add
    -- 110 sub
    -- 000 and
    -- 001 or
    -- 111 slt set less than
    mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
    mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
    mux3: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>d, x=>x3);
    add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
    sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
    and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
    or1: or32 PORT MAP (a=>a, b=>b, c=>cor);

    z1 <= (not s (2) and s (1) and not s (0));
    z2 <= (s(2) and s(1) and not s(0));
    z3 <= (not s (2) and not s (1) and not s (0));
    z4 <= (not s (2) and not s (1) and s (0));

    --
    -- z4  z3  z2  z1       x3  x2  x1
    -- 0   0   0   1        0   x   0
    -- 0   0   1   0        0   x   1
    -- 0   1   0   0        1   1   x
    -- 1   0   0   0        1   0   x

    -- x3 <= z3 or z4
    -- x2 <= z3
    -- x1 <= z2

    x3 <= z3 or z4;
    x2 <= z3;
    x1 <= z2;
    sadd <= '0';
    c <= d;
    nul <= d (31);
    testnull: FOR i IN 30 DOWNTO 0 GENERATE
        nul <= d (i) nor nul;
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;


    entity opdecode is
    port (
        opcode: in std_logic_vector (5 downto 0);
        memtoreg: out std_logic;
        memwrite: out std_logic;
        branch: out std_logic;
        alusrc: out std_logic;
        regdst: out std_logic;
        regwrite: out std_logic;
        aluop: out std_logic_vector (1 downto 0)
    );
    end;

    architecture behaviour of opdecode is
    begin

    end;

library ieee;
use ieee.std_logic_1164.all;


    entity funcdecode is
    port (
        aluop: in std_logic_vector (1 downto 0);
        func: in std_logic_vector (5 downto 0);
        aluoperation: out std_logic_vector (2 downto 0)
    );
    end;

    architecture behaviour of funcdecode is
    begin

    end;

library ieee;
use ieee.std_logic_1164.all;


    entity Bit2Shift is
    port (
        a: in std_logic_vector (31 downto 0);
        b: out std_logic_vector (31 downto 0)
    );
    end;

    architecture behaviour of Bit2Shift is
    begin
        b   <=  a;
    end;

library ieee;
use ieee.std_logic_1164.all;


    entity signunit is
    port (
        a: in std_logic_vector (15 downto 0);
        b: out std_logic_vector (31 downto 0)
    );
    end;

    architecture behaviour of signunit is
    begin
        b <=   ('0','0','0','0',   '0','0','0','0',   '0','0','0','0',   '0','0','0','0', '0','0','0','0',   '0','0','0','0',   '0','0','0','0',   '0','0','0','0');
    end;


library ieee;
use ieee.std_logic_1164.all;

entity mips32 is
port (
    globalCPUCLK: in std_logic
);
end;

architecture behaviour of mips32 is
    component registerset32_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (4 downto 0);
        regsrc2: in std_logic_vector (4 downto 0);
        regdest: in std_logic_vector (4 downto 0);
        en: in std_logic
    );
    end component;

    component ALU
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic_vector (2 downto 0);
        t: out std_logic;
        nul: inout std_logic;
        globalcarryflag: out std_logic
    );
    end component;

    -- 4 x MUX

    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;

    component MUX5_2_1
    port (
        c: out std_logic_vector (4 downto 0);
        b: in std_logic_vector (4 downto 0);
        a: in std_logic_vector (4 downto 0);
        x: in std_logic
    );
    end component;

    -- befehlszaehler, addierer + 4 u Sprung 2x Addierer

    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;

    component Bit2Shift
    port (
        a: in std_logic_vector (31 downto 0);
        b: out std_logic_vector (31 downto 0)
    );
    end component;

    component signunit
    port (
        a: in std_logic_vector (15 downto 0);
        b: out std_logic_vector (31 downto 0)
    );
    end component;

    component sram
    port (
        en: in std_logic;
        addrs: in std_logic_vector (31 downto 0);
        writedata: in std_logic_vector (31 downto 0);
        readdata: out std_logic_vector (31 downto 0)
    );
    end component;

    component prom
    port (
        addrs: in std_logic_vector (31 downto 0);
        readdata: out std_logic_vector (31 downto 0)
    );
    end component;

    component reg32
    port (
        q: out std_logic_vector (31 downto 0);
        d: in std_logic_vector (31 downto 0);
        c: in std_logic
    );
    end component;

    component opdecode
    port (
        opcode: in std_logic_vector (5 downto 0);
        memtoreg: out std_logic;
        memwrite: out std_logic;
        branch: out std_logic;
        alusrc: out std_logic;
        regdst: out std_logic;
        regwrite: out std_logic;
        aluop: out std_logic_vector (1 downto 0)
    );
    end component;

    component funcdecode
    port (
        aluop: in std_logic_vector (1 downto 0);
        func: in std_logic_vector (5 downto 0);
        aluoperation: out std_logic_vector (2 downto 0)
    );
    end component;

    signal op: std_logic_vector (31 downto 0);

    signal aluop: std_logic_vector (1 downto 0);
    signal func: std_logic_vector (5 downto 0);
    signal aluoperation: std_logic_vector (2 downto 0);
    signal memtoreg: std_logic;
    signal memwrite: std_logic;
    signal branch: std_logic;
    signal alusrc: std_logic;
    signal regdst: std_logic;
    signal regwrite: std_logic;

    signal pcsrc: std_logic;

    signal regdest: std_logic_vector (4 downto 0);
    signal aALUOperandBus, bALUOperandBUS, cALUOperandBus: std_logic_vector (31 downto 0);
    signal signunitBUS: std_logic_vector (31 downto 0);
    signal memReadData: std_logic_vector (31 downto 0);
    signal destdata: std_logic_vector (31 downto 0);
    signal srcdata1: std_logic_vector (31 downto 0);
    signal srcdata2: std_logic_vector (31 downto 0);

    signal nulbit: std_logic;

    signal pcBUSplus: std_logic_vector (31 downto 0);
    signal pcBUS: std_logic_vector (31 downto 0);

    signal Value32_4: std_logic_vector (31 downto 0);

    signal add1cBus: std_logic_vector (31 downto 0);
    signal add2cBus: std_logic_vector (31 downto 0);

    signal Bit2ShiftBus: std_logic_vector (31 downto 0);

    signal Value1_0: std_logic;

    signal nullbit: std_logic;


begin
    funcdecode1: funcdecode PORT MAP (aluoperation=>aluoperation,func=>func,aluop=>aluop);
    opdecode1: opdecode PORT MAP (opcode=>op(31 downto 26), aluop=>aluop, memtoreg => memtoreg, memwrite => memwrite, branch => branch, alusrc => alusrc, regdst => regdst, regwrite => regwrite);


    mux1: MUX5_2_1 PORT MAP (a=>op (20 downto 16), b=> op (15 downto 11), c=>regdest, x=>regdst);
    mux2: MUX32_2_1 PORT MAP (a=>srcdata1, b=>signunitBUS, c=>bALUOperandBUS, x=>alusrc);
    mux3: MUX32_2_1 PORT MAP (a=>cALUOperandBus, b=>memReadData, c=>destdata, x=>memtoreg);
    mux4: MUX32_2_1 PORT MAP (b=>add2cBus, a=>add1cBus, c=>pcBUSplus, x=>pcsrc);

    signunit1: signunit PORT MAP (a=>op (15 downto 0), b=>signunitBUS);
    Bit2Shift1: Bit2Shift PORT MAP (a=>signunitBUS, b=>Bit2ShiftBUS);

    add1: ripplecarrychainadder32 PORT MAP (a=>pcBUS, b=>Value32_4, c=>add1cBus, s=>Value1_0);
    add2: ripplecarrychainadder32 PORT MAP (a=>Bit2ShiftBus, b=>add1cBUS, c=>add2cBUS, s=>Value1_0);

    pc: reg32 PORT MAP (q=>pcBUS, d=>pcBUSplus, c=>globalCPUCLK);

    alu1: alu PORT MAP (a=>srcdata1, b=>bALUOperandBUS, c=>cALUOperandBus, s=>aluoperation, nul=>nullbit);
    regset1: registerset32_32 PORT MAP (regdest=>regdest, destdata=>destdata, srcdata1=>srcdata1, srcdata2=>srcdata2, en=>regwrite, regsrc1=>op (25 downto 21), regsrc2=>op (20 downto 16));

    sram1: sram PORT MAP (en=>memwrite, addrs=>cALUOperandBus, writedata=>srcdata2, readdata=>memReadData);
    prom1: prom PORT MAP (addrs=>pcBUS, readdata=>op);

    pcsrc <= nullbit and branch;

    Value32_4 <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
    Value1_0 <= '0';

    op (25 downto 21) <= ('0','0','0','0','0');
    op (20 downto 16) <= ('0','0','0','0','0');
    regdest <= ('0','0','0','0','0') after 0 ns, ('0','0','0','0','0') after 3 ns;
    regwrite <= '0' after 0 ns, '1' after 1 ns, '0' after 2 ns, '0' after 3 ns, '1' after 4 ns, '0' after 5 ns;
    destdata <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0') after 0 ns;
end;

So, also jetzt funktioniert die Sache schon 100-prozentig und lässt sich übersetzen. Deswegen tut die Sache nur der Unterschied ist halt, dass also die Befehle noch nicht implementiert sind. Jetzt müssen wir den Datenspeicher nicht implementieren weil wir haben ihm nur zwei Befehle. Uns ist eines in Addition, Befehl und das andere ist ein Datentransfer Befehl mit konstanten so und da brauchen wir den Datenspeicher nicht weil es findet in den Registern statt und deswegen hab ich da einfach ein leeres Ding gemacht was einfach nichts wiedergibt. Das ist eine und das andere ist der Befehl Dekodierung Funktion dekodieren, die sind ganz schnell umgesetzt. Die müssen ja sozusagen nur genau zwei Befehle herhalten und die müssen einfach wenn der Befehl reinkommt. Entsprechend müssen müssen Sie entsprechend umsetzen. Ist nicht besonders schwierig ebenso muss genau dieser Befehl von dem ich gerade geredet hat muss dann in den Programm Speicher der muss dann da hintereinander rein aber da muss man keine komplizierten Register benutzen, weil da kann man einfach Tupel nehmen weil mit diesem Tupel, die braucht man einfach nach den Reihen nach wiederzugeben. Ein bisschen umständlich ist es. Ich mach maximal acht Befehle wenn man muss sozusagen dann bei acht Befehlen drei bitte abfragen und dann entsprechend das entsprechende wiedergeben. So das ist das eine und das andere ist, dann müsste man halt sehen, dass in Registers Satz addiert wurde entsprechend und dann kommt noch das letzte das muss unbedingt unbedingt rein bei dem Befehl Reset sonst wird die Sache nicht funktionieren. Das mache ich mit After wie sonst auch das also zu sagen die einzelnen Bit sozusagen nach einem gewissen Zeit abstehenden, sozusagen dann erst mal in die Register eins nach dem anderen auf null gesetzt werden sonst kommt's nachher zu Komplikationen und das muss man als erstes durchlaufen lassen und dann kann man nach und nach die Befehle abfragen

https://opencores.org/projects/plasma/opcodes
Hier sind die OpCodes, das setze ich jetzt um, und - ich nehme addi, das kann ich zu 0 addieren, damit - weil ich kein li benutze.

Geht mit addi nicht ist es richtig, dass in der zwei Register das ist schon klar

Geht anders, obwohl die Komponenten Verschaltet sind kann ich auf das Signal sozusagen von außen oder zwischendrin zugreifen und es dann initialisieren und dann kann ich auch einen einzigen@Befehl sozusagen also add umsetzen und dann musst es schon gehen

Also das Problem ist es geht so nicht das ist das Problem weil wenn ich das jetzt intern setze, dann wird es trotzdem nicht gesetzt bleiben weil das führt ihn wieder zurück

Mich jetzt einen Trick bedient erst mal war and und or falsch codiert Zweitens hab ich das logische und so gemacht das ist einfach alles auf Null setzt und bisher sieht's gut aus.

Okay, das Ding ist okay. Also erst mal funktioniert sagen wir so da hat sich ein ganz kleiner Fehler eingeschlichen in den gesamten Quelltext. Da ist sagen wir also nicht im Quelltext aber in dem in dem ganzen Blogdiagramm ist ein Fehler. Wenn sie den finden, dann garantiere ich Ihnen Sind Sie mindestens so gut wie ich, dass sie das in VHDL hinschreiben, oder sie sind so gut, dass sie sich das angucken und den VHDL in ihrem Kopf und dabei haben sie auf einmal alles in ihrem Blick. Ich kann ihn erklären das ist ein klitzekleines Problem. Gibt ne kleine Abweichung brauchen Sie. Ich gebe Ihnen Tipp, wenn Sie den Kurs studiert haben, dann können Sie das Wort Zustandselemente und sie müssen sich da keine Sorgen machen.
Eines kann ich Ihnen garantieren den Datenpfad, den ich haben wollte den hat es zu 100 % bedient dass es sicher es hat das getan, was zu tun ist, in dem ich nämlich durch die alu etwas durchgeschickt habe in dem sie die Steuer Wort übernommen hat. Aber denken Sie nach, wo ist der Fehler ich meine sagen wir mal so das Programm würde mit der gewissen abwechslungsreich befehlen wird es Anfang das Richtige zu tun, wenn sie Abwechslung in den Arbeitsspeicher schreiben und Abwechselnd in die Register dann werden Sie das Problem wahrscheinlich los und wahrscheinlich viele Probleme. hinkriegen beim Programmieren ich sag ihm so ein garantieren, dass ein Schaltwerk nicht so funktioniert, wenn sie einmal eins anlegen dann läuft das Ding weiter. Sie müssen immer damit rechnen so sehr sie das Wort wahrscheinlich rising Edge und falling Edge, das ist nichts besonderes das hat nicht die Bedeutung, wie man manchmal malen könnte. Das ist keine Fuzzi Logik. Müsste sich keine Gedanken drüber Sanson Fehler nur wissen Sie Schaltwerk hat halt zwei Zustände. Die müssen rauf und runtergehen. Jetzt singen sie mal nach, was passieren würde. Selbst wenn sie den Takt anlegen dann passiert was ganz komisches. Wenn sie nämlich ist, den Befehl Dekoda nicht mit dem Takt bedienen also den Befehl die Coder der Wechsel zwar jetzt Schöner Weise das Wasser ausgibt, aber unter Umständen bleibt halt das EN also des WE an unserem Registers Satz, ständig eins und wissen Sie, was das vom Schaltwerk bedeutet das ist nämlich das verrückte an der Geschichte. Eigentlich könnten wir ja meinen unter Schaller arbeitet gar nicht. Nein das stimmt nicht. Unser Befehl Speicher läuft mit jedem Takt immer weiter das besteht auch nicht die Gefahr. Letztenendes wenden unser Befehl speicher denn ein einen Takt hätte das hat er in dem Fall nicht, der bei rauf den Befehl liefert und dann bitteschön übernimmt. Ein Flipflop hat immer zwei Zustände, unterscheidet es massiv von anderen. Sie müssen den Clock einspeisen und wenn sie runtergehen dann so und es fehlt übrigens auch an unserem Befehl Speicher in diesem Falle würde der durchlaufen.
soll nicht passieren umgekehrt. Wenn er das nicht tut, dann müssen Sie keine Sorge haben dann geht ein Befehl nach dem anderen Takt für Takt. Das macht es von alleine. Jetzt haben sie aber ein Problem. Jetzt denken Sie nachher, sie müssen die Alu rauf und runter schalten nein, müssen Sie alles nicht machen das einzige was in unserem komplexen Schaltwerk unter Computer ist ja sozusagen komplexe Schaltwerk mit einer Besonderheit. Es ist ein Operations Werk des arbeitet nach dem Prinzip, das ist universell ist und damit ein Rechenwerk d.h. es hat ein eine ALU und ein Registers, Satz und Leitwerk ist einfach ein Umschalt Barez steuerwerk dadurch dass Befehle versteht gut jetzt passiert aber gar nicht viel weil sie haben halt ihre Zustandselemente reißen die das sind also unsere Register und das ist unser Arbeitsspeicher. Aber der hat ein Problem das ist halt auch ein Speicher und der geht rauf und runter und wenn er das nicht tut, dann übernimmt er keine Daten nicht nur dass er die zwar übernimmt und die nicht ankommen. Das funktioniert alles fabelhaft. Aber erst wenn wieder das Low erreicht ist, werden die Daten dann übernommen und es fehlt an der Sache, weil unser Befehl dekodieren das hab ich jetzt in Ordnung gebracht. Der hat leider keinen Eingang für einen Takt und das ist nicht gut weil sie müssen sozusagen eine logische Umschaltung machen, dass jedes Mal wenn der Takt nach oben geht dann schaltet das IN oder das WE egal wo auf nullbeziehungsweise auf eins also dann geht's auf eins nach oben und wenn der Takt aber wieder runtergeht, dann musst du es mitschwingen. Dann muss nämlich jedes WE wieder deaktiviert werden sonst funktioniert das nicht. Das hab ich jetzt gemacht und damit funktioniert der Prozessor eigentlich schon

Post by **david** » Wed Dec 04, 2024 10:59 pm

Code: Select all

-- (C) David Vajda
-- MIPS32 - minimal
-- 2024-12-04

library ieee;
use ieee.std_logic_1164.all;

entity rslatch is
port (
    r: in std_logic;
    s: in std_logic;
    q: inout std_logic;
    p: inout std_logic
);
end;

architecture behaviour of rslatch is
begin
    q   <=  (r nor p);
    p   <=  (s nor q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity clktriggeredrslatch is
port (
    r: in std_logic;
    s: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of clktriggeredrslatch is
    component rslatch
    port (
        r: in std_logic;
        s: in std_logic;
        q: inout std_logic;
        p: inout std_logic
    );
    end component;
    signal e, d: std_logic;
begin
    rs: rslatch PORT MAP (r=>e, s=>d, q=>q);
    d <= c and s;
    e <= c and r;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dlatch is
    component clktriggeredrslatch
    port (
        r: in std_logic;
        s: in std_logic;
        c: in std_logic;
        q: inout std_logic
    );
    end component;
    signal e, f: std_logic;
begin
    clkrs: clktriggeredrslatch PORT MAP (r=>f, s=>e, c=>c, q=>q);

    e <= d;
    f <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatchtestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dlatchtestbench is
    component dlatch
    port (
        c: in std_logic;
        d: in std_logic;
        q: inout std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dlatch PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (
    d: in std_logic;
    c: in std_logic;
    q: inout std_logic
);
end;

architecture behaviour of dff is
    component dlatch
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal e, a, b: std_logic;
begin
    d1: dlatch PORT MAP (c=>a, d=>e, q=>q);
    d2: dlatch PORT MAP (c=>b, d=>d, q=>e);
    a <= not c;
    b <= c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dfftestbench is
port (
    q: inout std_logic
);
end;

architecture behaviour of dfftestbench is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal d, c: std_logic;
begin
    dl: dff PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= '1' after 0 ns, '1' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity reg32 is
port (
    c: in std_logic;
    d: in std_logic_vector (31 downto 0);
    q: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of reg32 is
    component dff
    port (
        q: inout std_logic;
        d: in std_logic;
        c: in std_logic
    );
    end component;
    signal p: std_logic_vector (31 downto 0);
begin
    gen_reg: FOR i in 31 downto 0 generate
        dffx: dff PORT MAP (q=>p(i),d=>d(i),c=>c);
        q(i) <= p (i);
    end generate;
end;

library ieee;
use ieee.std_logic_1164.all;


entity dffregtestbench is
port (
    q: inout std_logic_vector (31 downto 0)
);
end;

architecture behaviour of dffregtestbench is
    component reg32
    port (
        q: out std_logic_vector (31 downto 0);
        d: in std_logic_vector (31 downto 0);
        c: in std_logic
    );
    end component;
    signal d: std_logic_vector (31 downto 0);
    signal c: std_logic;
begin
    r32: reg32 PORT MAP (d=>d, c=>c, q=>q);

-- diese sind aus dem letzten eingefuegt, damit ich sie nicht noch mal schreiben muss

    d <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 20 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 40 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 50 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 60 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1')  after 70 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 80 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 90 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 100 ns;
    c <= '1' after 0 ns, '0' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '0' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1 is
port (
    c: out std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX32_2_1 is
begin
    MUX_generate: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX5_2_1 is
port (
    c: out std_logic_vector (4 downto 0);
    b: in std_logic_vector (4 downto 0);
    a: in std_logic_vector (4 downto 0);
    x: in std_logic
);
end;

architecture behaviour of MUX5_2_1 is
begin
    MUX_generate: FOR i IN 4 DOWNTO 0 GENERATE
        c (i) <= (a (i) and not x) or (b (i) and x);
    END GENERATE;
end;


library ieee;
use ieee.std_logic_1164.all;

entity MUX32_2_1testbench is
port (
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of MUX32_2_1testbench is
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal b: std_logic_vector (31 downto 0);
    signal a: std_logic_vector (31 downto 0);
    signal x: std_logic;
begin
    mux: MUX32_2_1 PORT MAP (c=>c, b=>b, a=>a, x=>x);

    a <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0');
    b <= ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0');
    x <= '1' after 0 ns, '0' after 1 ns, '1' after 2 ns, '0' after 3 ns;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset2_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic;
    regsrc2: in std_logic;
    regdest: in std_logic;
    en: in std_logic
);
end;

architecture behaviour of registerset2_32 is
    component reg32
    port (
        c: in std_logic;
        d: in std_logic_vector (31 downto 0);
        q: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1 is
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal q1: std_logic_vector (31 downto 0);
    signal q2: std_logic_vector (31 downto 0);
    signal c1, c2: std_logic;
begin
    reg1: reg32 PORT MAP (q=>q1,d=>destdata,c=>c1);
    reg2: reg32 PORT MAP (q=>q2,d=>destdata,c=>c2);
    srcmux1: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata1, x=>regsrc1);
    srcmux2: MUX32_2_1 PORT MAP (a=>q1, b=>q2, c=>srcdata2, x=>regsrc2);
    c1 <= en and not regdest;
    c2 <= en and regdest;
end;

library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset2_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset2_32testbench is
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic;
    signal    regsrc2: std_logic;
    signal    regdest: std_logic;
    signal    en: std_logic;

begin
    regset_2_32: registerset2_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    regdest <= '0' after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
    regdest <= '0' after 0 ns;
    regsrc1 <= '0' after 0 ns;
    regsrc2 <= '0' after 0 ns;
end;

library ieee;
use ieee.std_logic_1164.all;


entity registerset4_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (1 downto 0);
    regsrc2: in std_logic_vector (1 downto 0);
    regdest: in std_logic_vector (1 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset4_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset2_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic;
        regsrc2: in std_logic;
        regdest: in std_logic;
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (1));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (1));
    reg1: registerset2_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en1, destdata=>destdata, regdest=>regdest (0));
    reg2: registerset2_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (0), regsrc2=>regsrc2 (0), en=>en2, destdata=>destdata, regdest=>regdest (0));
    en2 <= regdest (1) and en;
    en1 <= not regdest (1) and en;
end;


library ieee;
use ieee.std_logic_1164.all;
-- use std.textio.all;
-- use ieee.std_logic_textio.all;

entity registerset4_32testbench is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of registerset4_32testbench is
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal    destdata: std_logic_vector (31 downto 0);
    signal    regsrc1: std_logic_vector (1 downto 0);
    signal    regsrc2: std_logic_vector (1 downto 0);
    signal    regdest: std_logic_vector (1 downto 0);
    signal    en: std_logic;

begin
    regset_4_32: registerset4_32 PORT MAP (srcdata1=>srcdata1, srcdata2=>srcdata2, destdata=>destdata, regsrc1=>regsrc1, regsrc2=>regsrc2,  regdest=>regdest, en=>en);
    -- regdest  <= ('0','0') after 0 ns;
    destdata <= ('1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0', '1', '0') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','0','0','0') after 30 ns, ('1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0', '1', '1', '0', '0') after 40 ns, ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1') after 80 ns;
    en <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns, '0' after 120 ns;
    regdest <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('1', '0') after 100 ns;
    regsrc1 <= ('0','0') after 0 ns, ('0','1') after 30 ns, ('0','0') after 80 ns, ('0', '1') after 90 ns, ('1', '0') after 110 ns, ('0', '1') after 130 ns, ('1', '0') after 140 ns;
    regsrc2 <= ('0','0') after 0 ns, ('0','1') after 30 ns;
end;


library ieee;
use ieee.std_logic_1164.all;


entity registerset8_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (2 downto 0);
    regsrc2: in std_logic_vector (2 downto 0);
    regdest: in std_logic_vector (2 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset8_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset4_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (1 downto 0);
        regsrc2: in std_logic_vector (1 downto 0);
        regdest: in std_logic_vector (1 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (2));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (2));
    reg1: registerset4_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (1 downto 0));
    reg2: registerset4_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (1 downto 0), regsrc2=>regsrc2 (1 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (1 downto 0));
    en2 <= regdest (2) and en;
    en1 <= not regdest (2) and en;
end;


library ieee;
use ieee.std_logic_1164.all;

entity registerset16_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (3 downto 0);
    regsrc2: in std_logic_vector (3 downto 0);
    regdest: in std_logic_vector (3 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset16_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset8_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (2 downto 0);
        regsrc2: in std_logic_vector (2 downto 0);
        regdest: in std_logic_vector (2 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (3));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (3));
    reg1: registerset8_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (2 downto 0));
    reg2: registerset8_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (2 downto 0), regsrc2=>regsrc2 (2 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (2 downto 0));
    en2 <= regdest (3) and en;
    en1 <= not regdest (3) and en;
end;

library ieee;
use ieee.std_logic_1164.all;

entity registerset32_32 is
port (
    srcdata1: out std_logic_vector (31 downto 0);
    srcdata2: out std_logic_vector (31 downto 0);
    destdata: in std_logic_vector (31 downto 0);
    regsrc1: in std_logic_vector (4 downto 0);
    regsrc2: in std_logic_vector (4 downto 0);
    regdest: in std_logic_vector (4 downto 0);
    en: in std_logic
);
end;

architecture behaviour of registerset32_32 is
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    component registerset16_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (3 downto 0);
        regsrc2: in std_logic_vector (3 downto 0);
        regdest: in std_logic_vector (3 downto 0);
        en: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal en1, en2: std_logic;
    signal srcdata1_1: std_logic_vector (31 downto 0);
    signal srcdata1_2: std_logic_vector (31 downto 0);
    signal srcdata2_1: std_logic_vector (31 downto 0);
    signal srcdata2_2: std_logic_vector (31 downto 0);
begin
    mux1: MUX32_2_1 PORT MAP (a=>srcdata1_1, b=>srcdata1_2, c=>srcdata1, x=>regsrc1 (4));
    mux2: MUX32_2_1 PORT MAP (a=>srcdata2_1, b=>srcdata2_2, c=>srcdata2, x=>regsrc2 (4));
    reg1: registerset16_32 PORT MAP (srcdata1=>srcdata1_1, srcdata2=>srcdata2_1, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en1, destdata=>destdata, regdest=>regdest (3 downto 0));
    reg2: registerset16_32 PORT MAP (srcdata1=>srcdata1_2, srcdata2=>srcdata2_2, regsrc1=>regsrc1 (3 downto 0), regsrc2=>regsrc2 (3 downto 0), en=>en2, destdata=>destdata, regdest=>regdest (3 downto 0));
    en2 <= regdest (4) and en;
    en1 <= not regdest (4) and en;
end;

-- (C) David Vajda
-- 32 Bit Ripple Carry Chain Adder / Subtrahierer / Volladdierer
-- 2024-12-02

library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
port (
    a: in std_logic;
    b: in std_logic;
    c: out std_logic;
    s: in std_logic;
    t: out std_logic
);
end;

architecture behaviour of fulladder is
begin
    c <= a xor b xor s;
    t <= (a and b) or ((a or b) and s);
end;

library ieee;
use ieee.std_logic_1164.all;

entity ripplecarrychainadder32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    s: in std_logic;
    t: out std_logic
);
end;

architecture behaviour of ripplecarrychainadder32 is
    component fulladder
    port (
        a: in std_logic;
        b: in std_logic;
        c: out std_logic;
        s: in std_logic;
        t: out std_logic
    );
    end component;
    signal x: std_logic_vector (32 downto 0);
begin
        fa_loop: FOR i IN 31 DOWNTO 0 GENERATE
            fa: fulladder PORT MAP (a=>a(i), b=>b(i), c=>c(i), s=>x(i), t=>x(i+1));
        END GENERATE;
        t <= x (32) ;
        x (0) <= s;
    --fa3: fulladder20241128 PORT MAP (a=>a3, b=>b3, c=>c3, s=>s3, t=>t);
    --fa2: fulladder20241128 PORT MAP (a=>a2, b=>b2, c=>c2, s=>s2, t=>s3);
    --fa1: fulladder20241128 PORT MAP (a=>a1, b=>b1, c=>c1, s=>s1, t=>s2);
    --fa0: fulladder20241128 PORT MAP (a=>a0, b=>b0, c=>c0, s=>s, t=>s1);
end;

library ieee;
use ieee.std_logic_1164.all;

entity ripplecarrychainadder32testbench is
port (
    c: out std_logic_vector (31 downto 0);
    t: out std_logic
);
end;


architecture behaviour of ripplecarrychainadder32testbench is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    signal a: std_logic_vector (31 downto 0);
    signal b: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    rplcadd: ripplecarrychainadder32 PORT MAP (c=>c, b=>b, a=>a, s=>s, t=>t);
    -- 19219 + 14823 = 34042
    -- 0b100101100010011 + 0b11100111100111 = 0b1000010011111010
    a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;

    b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
    s <= '0';
end;

library ieee;
use ieee.std_logic_1164.all;

entity com32 is
port (
    x: in std_logic_vector (31 downto 0);
    y: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of com32 is
begin
        com_connect: FOR i IN 31 DOWNTO 0 GENERATE
                y (i) <= not x (i);
        END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity neg32 is
port (
    b: out std_logic_vector (31 downto 0);
    a: in std_logic_vector (31 downto 0);
    t: out std_logic
);
end;

architecture behaviour of neg32 is
    component com32
    port (
        x: in std_logic_vector (31 downto 0);
        y: out std_logic_vector (31 downto 0)
    );
    end component;

    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    signal c: std_logic_vector (31 downto 0);
    signal d: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    neg32_generate_1: FOR i IN 31 DOWNTO 0 GENERATE
        d (i) <= '0';
    END GENERATE;
    s <= '1';
    com: com32 PORT MAP (x=>a, y=>c);
    add: ripplecarrychainadder32 PORT MAP (b=>d, a=>c, s=>s, t=>t, c=>b);
end;

library ieee;
use ieee.std_logic_1164.all;

entity sub32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    t: out std_logic
);
end;

architecture behaviour of sub32 is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component neg32
    port (
        b: out std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    signal x: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    neg: neg32 PORT MAP (a=>a, b=>x);
    add: ripplecarrychainadder32 PORT MAP (b=>b, a=>x, c=>c, s=>s, t=>t);
    s <= '0';
end;

library ieee;
use ieee.std_logic_1164.all;

entity sub32testbench is
port (
    c: out std_logic_vector (31 downto 0);
    t: out std_logic
);
end;


architecture behaviour of sub32testbench is
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    signal a: std_logic_vector (31 downto 0);
    signal b: std_logic_vector (31 downto 0);
    signal s: std_logic;
begin
    sub: sub32 PORT MAP (a=>a, b=>b, c=>c, t=>t);

    a <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 0 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 20 ns;
    b <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','1','1', '1','0','0','1', '1','1','1','0', '0','1','1','1') after 0 ns,  ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 10 ns, ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','1','0','0', '1','0','1','1', '0','0','0','1' ,'0','0','1','1') after 20 ns;
    s <= '0' after 0 ns, '1' after 10 ns;
    -- 19219 - 14823 =
end;

library ieee;
use ieee.std_logic_1164.all;

entity or32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of or32 is
begin
    genor32: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= b (i) or a (i);
    END GENERATE;
end;


library ieee;
use ieee.std_logic_1164.all;

entity and32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of and32 is
begin
    genand32: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= '0';
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;


    entity sram is
    port (
        en: in std_logic;
        addrs: in std_logic_vector (31 downto 0);
        writedata: in std_logic_vector (31 downto 0);
        readdata: out std_logic_vector (31 downto 0)
    );
    end;

    architecture behaviour of sram is
    begin
        readdata <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
    end;


library ieee;
use ieee.std_logic_1164.all;


    entity prom is
    port (
        addrs: in std_logic_vector (31 downto 0);
        readdata: out std_logic_vector (31 downto 0)
    );
    end;

    architecture behaviour of prom is
    begin
        readdata <= ('0','0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '0','0','0','0','0', '1','0','0','1','0','0');
    end;


library ieee;
use ieee.std_logic_1164.all;

entity ALU is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    s: in std_logic_vector (2 downto 0);
    t: out std_logic;
    nul: inout std_logic;
    globalcarryflag: out std_logic
);
end;

architecture behaviour of ALU is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    component and32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component or32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal z4, z3, z2, z1: std_logic;
    signal x3, x2, x1: std_logic;
    signal csub: std_logic_vector (31 downto 0);
    signal cor: std_logic_vector (31 downto 0);
    signal cmux1: std_logic_vector (31 downto 0);
    signal cmux2: std_logic_vector (31 downto 0);
    signal cadd: std_logic_vector (31 downto 0);
    signal cand:  std_logic_vector (31 downto 0);
    signal sadd: std_logic;
    signal d: std_logic_vector (31 downto 0);
begin
    -- 010 add
    -- 110 sub
    -- 000 and
    -- 001 or
    -- 111 slt set less than
    mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
    mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
    mux3: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>d, x=>x3);
    add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
    sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
    and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
    or1: or32 PORT MAP (a=>a, b=>b, c=>cor);

    z1 <= (not s (2) and s (1) and not s (0));
    z2 <= (s(2) and s(1) and not s(0));
    z3 <= (not s (2) and not s (1) and not s (0));
    z4 <= (not s (2) and not s (1) and s (0));

    --
    -- z4  z3  z2  z1       x3  x2  x1
    -- 0   0   0   1        0   x   0
    -- 0   0   1   0        0   x   1
    -- 0   1   0   0        1   0   x
    -- 1   0   0   0        1   1   x

    -- x3 <= z3 or z4
    -- x2 <= z3
    -- x1 <= z2

    x3 <= z3 or z4;
    x2 <= z4;
    x1 <= z2;
    sadd <= '0';
    c <= d;
    nul <= d (31);
    testnull: FOR i IN 30 DOWNTO 0 GENERATE
        nul <= d (i) nor nul;
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;


    entity opdecode is
    port (
        opcode: in std_logic_vector (5 downto 0);
        memtoreg: out std_logic;
        memwrite: out std_logic;
        branch: out std_logic;
        alusrc: out std_logic;
        regdst: out std_logic;
        regwrite: out std_logic;
        aluop: out std_logic_vector (1 downto 0);
        cpuclock: in std_logic
    );
    end;

    architecture behaviour of opdecode is
    begin
        memtoreg <= '0';
        memwrite <= '0';
        branch <= '0';
        alusrc <= '0';
        regdst <= '1';
        regwrite <= '1' and cpuclock;
    end;

library ieee;
use ieee.std_logic_1164.all;


    entity funcdecode is
    port (
        aluop: in std_logic_vector (1 downto 0);
        func: in std_logic_vector (5 downto 0);
        aluoperation: out std_logic_vector (2 downto 0)
    );
    end;

    architecture behaviour of funcdecode is
    begin
        aluoperation <= ('0', '0', '0');
    end;

library ieee;
use ieee.std_logic_1164.all;


    entity Bit2Shift is
    port (
        a: in std_logic_vector (31 downto 0);
        b: out std_logic_vector (31 downto 0)
    );
    end;

    architecture behaviour of Bit2Shift is
    begin
        b   <=  a;
    end;

library ieee;
use ieee.std_logic_1164.all;


    entity signunit is
    port (
        a: in std_logic_vector (15 downto 0);
        b: out std_logic_vector (31 downto 0)
    );
    end;

    architecture behaviour of signunit is
    begin
        b <=   ('0','0','0','0',   '0','0','0','0',   '0','0','0','0',   '0','0','0','0', '0','0','0','0',   '0','0','0','0',   '0','0','0','0',   '0','0','0','0');
    end;


library ieee;
use ieee.std_logic_1164.all;

entity mips32 is
port (
    globalCPUCLK: in std_logic
);
end;

architecture behaviour of mips32 is
    component registerset32_32
    port (
        srcdata1: out std_logic_vector (31 downto 0);
        srcdata2: out std_logic_vector (31 downto 0);
        destdata: in std_logic_vector (31 downto 0);
        regsrc1: in std_logic_vector (4 downto 0);
        regsrc2: in std_logic_vector (4 downto 0);
        regdest: in std_logic_vector (4 downto 0);
        en: in std_logic
    );
    end component;

    component ALU
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic_vector (2 downto 0);
        t: out std_logic;
        nul: inout std_logic;
        globalcarryflag: out std_logic
    );
    end component;

    -- 4 x MUX

    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;

    component MUX5_2_1
    port (
        c: out std_logic_vector (4 downto 0);
        b: in std_logic_vector (4 downto 0);
        a: in std_logic_vector (4 downto 0);
        x: in std_logic
    );
    end component;

    -- befehlszaehler, addierer + 4 u Sprung 2x Addierer

    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;

    component Bit2Shift
    port (
        a: in std_logic_vector (31 downto 0);
        b: out std_logic_vector (31 downto 0)
    );
    end component;

    component signunit
    port (
        a: in std_logic_vector (15 downto 0);
        b: out std_logic_vector (31 downto 0)
    );
    end component;

    component sram
    port (
        en: in std_logic;
        addrs: in std_logic_vector (31 downto 0);
        writedata: in std_logic_vector (31 downto 0);
        readdata: out std_logic_vector (31 downto 0)
    );
    end component;

    component prom
    port (
        addrs: in std_logic_vector (31 downto 0);
        readdata: out std_logic_vector (31 downto 0)
    );
    end component;

    component reg32
    port (
        q: out std_logic_vector (31 downto 0);
        d: in std_logic_vector (31 downto 0);
        c: in std_logic
    );
    end component;

    component opdecode
    port (
        opcode: in std_logic_vector (5 downto 0);
        memtoreg: out std_logic;
        memwrite: out std_logic;
        branch: out std_logic;
        alusrc: out std_logic;
        regdst: out std_logic;
        regwrite: out std_logic;
        aluop: out std_logic_vector (1 downto 0);
        cpuclock: in std_logic
    );
    end component;

    component funcdecode
    port (
        aluop: in std_logic_vector (1 downto 0);
        func: in std_logic_vector (5 downto 0);
        aluoperation: out std_logic_vector (2 downto 0)
    );
    end component;

    signal op: std_logic_vector (31 downto 0);

    signal aluop: std_logic_vector (1 downto 0);
    signal func: std_logic_vector (5 downto 0);
    signal aluoperation: std_logic_vector (2 downto 0);
    signal memtoreg: std_logic;
    signal memwrite: std_logic;
    signal branch: std_logic;
    signal alusrc: std_logic;
    signal regdst: std_logic;
    signal regwrite: std_logic;

    signal pcsrc: std_logic;

    signal regdest: std_logic_vector (4 downto 0);
    signal aALUOperandBus, bALUOperandBUS, cALUOperandBus: std_logic_vector (31 downto 0);
    signal signunitBUS: std_logic_vector (31 downto 0);
    signal memReadData: std_logic_vector (31 downto 0);
    signal destdata: std_logic_vector (31 downto 0);
    signal srcdata1: std_logic_vector (31 downto 0);
    signal srcdata2: std_logic_vector (31 downto 0);

    signal nulbit: std_logic;

    signal pcBUSplus: std_logic_vector (31 downto 0);
    signal pcBUS: std_logic_vector (31 downto 0);

    signal Value32_4: std_logic_vector (31 downto 0);

    signal add1cBus: std_logic_vector (31 downto 0);
    signal add2cBus: std_logic_vector (31 downto 0);

    signal Bit2ShiftBus: std_logic_vector (31 downto 0);

    signal Value1_0: std_logic;

    signal nullbit: std_logic;

    signal globalCPUC: std_logic;
begin
    funcdecode1: funcdecode PORT MAP (aluoperation=>aluoperation,func=>func,aluop=>aluop);
    opdecode1: opdecode PORT MAP (opcode=>op(31 downto 26), aluop=>aluop, memtoreg => memtoreg, memwrite => memwrite, branch => branch, alusrc => alusrc, regdst => regdst, regwrite => regwrite, cpuclock=>globalCPUC);


    mux1: MUX5_2_1 PORT MAP (a=>op (20 downto 16), b=> op (15 downto 11), c=>regdest, x=>regdst);
    mux2: MUX32_2_1 PORT MAP (a=>srcdata1, b=>signunitBUS, c=>bALUOperandBUS, x=>alusrc);
    mux3: MUX32_2_1 PORT MAP (a=>cALUOperandBus, b=>memReadData, c=>destdata, x=>memtoreg);
    mux4: MUX32_2_1 PORT MAP (b=>add2cBus, a=>add1cBus, c=>pcBUSplus, x=>pcsrc);

    signunit1: signunit PORT MAP (a=>op (15 downto 0), b=>signunitBUS);
    Bit2Shift1: Bit2Shift PORT MAP (a=>signunitBUS, b=>Bit2ShiftBUS);

    add1: ripplecarrychainadder32 PORT MAP (a=>pcBUS, b=>Value32_4, c=>add1cBus, s=>Value1_0);
    add2: ripplecarrychainadder32 PORT MAP (a=>Bit2ShiftBus, b=>add1cBUS, c=>add2cBUS, s=>Value1_0);

    pc: reg32 PORT MAP (q=>pcBUS, d=>pcBUSplus, c=>globalCPUC);

    alu1: alu PORT MAP (a=>srcdata1, b=>bALUOperandBUS, c=>cALUOperandBus, s=>aluoperation, nul=>nullbit);
    regset1: registerset32_32 PORT MAP (regdest=>regdest, destdata=>destdata, srcdata1=>srcdata1, srcdata2=>srcdata2, en=>regwrite, regsrc1=>op (25 downto 21), regsrc2=>op (20 downto 16));

    sram1: sram PORT MAP (en=>memwrite, addrs=>cALUOperandBus, writedata=>srcdata2, readdata=>memReadData);
    prom1: prom PORT MAP (addrs=>pcBUS, readdata=>op);

    pcsrc <= nullbit and branch;

    Value32_4 <= ('0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0', '0','0','0','0' ,'0','1','0','0');
    Value1_0 <= '0';

    globalCPUC <= '0' after 1 ns, '1' after 2 ns, '0' after 3 ns, '1' after 4 ns, '0' after 5 ns;
end;

Ist mir aufgefallen, ich hab gar nicht recht gehabt mir ist was aufgefallen. Ich hab nicht recht gehabt es war idiotisch können Sie aber so machen das war dumm von mir okay das war dumm von mir okay aber ich hab nicht hingeguckt hab nicht hingeguckt. Es war ein Fehler wissen. Wissen Sie, was das Dreieck soll als sie wussten schon okay das ist in Ordnung. Ich hab nicht hingeguckt entweder sie machen so oder so. So geht's natürlich auch. Warum soll man's nicht so machen jetzt hat halt mein Befehl Dekoda den Takt ist ja auch okay aber es steht eigentlich dran, dass sie lauter Dreiecke am Registers Satz ist. Ein Dreieck am Datenspeicher ist ein Dreieck. Ich mach immer in meine ganzen Speicher mache ich immer Dreiecke und ich hab's von der Schule nicht gesehen. Tut mir leid ich hab an jedes Register bisher immer Dreieck gemalt. Am Befehlszähler ist ein Dreieck hab ich nicht gesehen ja aber das sind lauter Dreiecke am Registers Satz ist ein Dreieck am Befehlszähler ist ein Dreieck. Unterm Datenspeicher ist ein Dreieck. Okay gut die sind da dann kann man's auch so machen. Dann kann man einfach an dieses Dreieck den Takt anlegen. Dann wird's genauso gut funktionieren. Ich hab's halt jetzt ans Befehls dekoder gemacht. Warum denn nicht vielleicht ne kleine Abweichung?

Das ganze kommt immer auf die Homepage und ich mach heut Nacht weiter dann passiert es was zu passieren hat nämlich folgendes. Ich werde die Register Zustandselemente und so weiter mit einem CLK versehen. Das ist auf diese Art und Weise geschieht und nicht wie ich das realisiert hatte darüber funktioniert ein Schaltwerk. Es hat mit dem Befehls dekodieren, nichts zu tun. Es muss man dann an der Stelle schon sehen, wenn man sagt, dass es damit nichts zu tun hat, weil die Schaltwerk realisiert sich von alleine durch die Zustandselemente und ihrem Takt. Dadurch wird es von alleine durchgeführt. Da braucht man keinen Takt im befehlsdekk Lutje. Das muss man einfach so sehen so jetzt ist es der Fall das muss man einfach so sehen. Schaltwerk wird schon alleine dadurch tun, dass die Zustandselemente einen Takt haben und man braucht dann diesen vermeintlichen Takt im Befehl dekodieren einfach nicht. Teil eines Schalt Wages. Ist das sowas notwendig wäre. Das Schaltwerk funktioniert mit den Zustandselementen. So von alleine und das ist mal das erste und Nummer zwei Nummer zwei werde ich dann alle Register mit einem internen Reset verbinden, der wenn man sich aktiviert, alle Register dann auf null zurück setzt

www.ituenix.de

MIPS32 in VHDL

MIPS32 in VHDL

Re: MIPS32 in VHDL

Re: MIPS32 in VHDL

Re: MIPS32 in VHDL

Re: MIPS32 in VHDL

Re: MIPS32 in VHDL

Re: MIPS32 in VHDL

Re: MIPS32 in VHDL

Re: MIPS32 in VHDL

Re: MIPS32 in VHDL