0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
0 0 0 0 0 1
2 0 0 1 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
2 0 0 1 0 1
Gruppe 2:
5 0 1 0 1 1
6 0 1 1 0 1
Gruppe 3:
7 0 1 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
0:2 0 0 - 0
2:6 0 - 1 0
5:7 0 1 - 1
5:13 - 1 0 1
6:7 0 1 1 -
7:15 - 1 1 1
13:15 1 1 - 1
14:15 1 1 1 -
6:7 0 1 1 -
14:15 1 1 1 -
0:2 0 0 - 0
5:7 0 1 - 1
13:15 1 1 - 1
2:6 0 - 1 0
5:13 - 1 0 1
6:13 - 1 0 1
7:15 - 1 1 1
Gruppe 2:
6:7 0 1 1 -
Gruppe 3:
14:15 1 1 1 -
Gruppe 0:
0:2 0 0 - 0
Gruppe 2:
5:7 0 1 - 1
Gruppe 3:
13:15 1 1 - 1
2:6 0 - 1 0
Gruppe 2:
5:13 - 1 0 1
Gruppe 3:
7:15 - 1 1 1
6:7:14:15 - 1 1 -
0:2 0 0 - 0
5:7:13:1 - 1 - 1
2:6 0 - 1 0
5:13:7:15 - 1 - 1
0 1 2 5 6 7 13 14 15
6:7:14:15 * * * *
0:2 * *
5:7:13:1 * * * *
2:6 * *
5:13:7:15 * * * *
0 1 2 5 6 7 13 14 15
6:7:14:15 * * * *
0:2 * *
5:7:13:1 * * * *
y <= (x2 and x1) or (not x3 and not x2 and not x0) or (x2 and x0)
entity meinschaltnetz is
port
(
x3, x2, x1, x0: in bit;
y: out bit
);
end;
architecture verhalten of meinschaltnetz is
begin
y <= (x2 and x1) or (not x3 and not x2 and not x0) or (x2 and x0);
end;