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Nächste Seite: Re: Aufgaben und Übungen, Aufwärts: Graphen, Schaltwerke und Zahlen Vorherige Seite: Re: Aufgaben und Übungen,

Re: Aufgaben und Übungen, 

	b a x	b a y
0	0 0 0	1 0 0
1	0 0 1	0 1 1
2	0 1 0	1 0 1
3	0 1 1	1 1 0
4	1 0 0	0 1 0
5	1 0 1	1 0 0
6	1 1 0	0 1 1
7	1 1 1	1 1 1


	b a x	b
0	0 0 0	1
1	0 0 1	0
2	0 1 0	1
3	0 1 1	1
4	1 0 0	0
5	1 0 1	1
6	1 1 0	0
7	1 1 1	1

	b a x	a
0	0 0 0	0
1	0 0 1	1
2	0 1 0	0
3	0 1 1	1
4	1 0 0	1
5	1 0 1	0
6	1 1 0	1
7	1 1 1	1

	b a x	y
0	0 0 0	0
1	0 0 1	1
2	0 1 0	1
3	0 1 1	0
4	1 0 0	0
5	1 0 1	0
6	1 1 0	1
7	1 1 1	1



	b a x	b
0	0 0 0	1
2	0 1 0	1
3	0 1 1	1
5	1 0 1	1
7	1 1 1	1

	b a x	a
1	0 0 1	1
3	0 1 1	1
4	1 0 0	1
6	1 1 0	1
7	1 1 1	1

	b a x	y
1	0 0 1	1
2	0 1 0	1
6	1 1 0	1
7	1 1 1	1



	b a x	b
Gruppe 0:
0	0 0 0	1
Gruppe 1:
2	0 1 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1
Gruppe 3:
7	1 1 1	1

	b a x	a
Gruppe 1:
1	0 0 1	1
4	1 0 0	1
Gruppe 2:
3	0 1 1	1
6	1 1 0	1
Gruppe 3:
7	1 1 1	1

	b a x	y
Gruppe 1:
1	0 0 1	1
2	0 1 0	1
Gruppe 2:
6	1 1 0	1
Gruppe 3:
7	1 1 1	1



	b a x	b
Gruppe 0:
0	0 0 0	1
Gruppe 1:
2	0 1 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1
Gruppe 3:
7	1 1 1	1

0:2			0 - 0
2:3			0 1 -
3:7			- 1 1
5:7			1 - 1


2:3			0 1 -
0:2			0 - 0
5:7			1 - 1
3:7			- 1 1

		0	2	3	5	7
2:3			*	*
0:2		*	*
5:7					*	*
3:7				*		*

		0	2	3	5	7
2:3			*	*
0:2		*	*
5:7					*	*

2:3			0 1 -
0:2			0 - 0
5:7			1 - 1

	bout <= (not b and a) or
			(not b and not x) or
			(b and x);
	bout <= not (
				(b or not a) and
				(b or x) and
				(not b or not x)
			);


	b a x	a
Gruppe 1:
1	0 0 1	1
4	1 0 0	1
Gruppe 2:
3	0 1 1	1
6	1 1 0	1
Gruppe 3:
7	1 1 1	1

1:3			0 - 1
4:6			1 - 0
3:7			- 1 1
6:7			1 1 -

3:7			- 1 1
1:3			0 - 1
4:6			1 - 0
6:7			1 1 -

		1	3	4	6	7
3:7			*			*
1:3		*	*
4:6				*	*
6:7					*	*

		1	3	4	6	7
3:7			*			*
1:3		*	*
4:6				*	*

3:7			- 1 1
1:3			0 - 1
4:6			1 - 0

		aout <= (a and x) or
			(not b and x) or
			(b and not x);
		aout <= not(
				(not a or not x) and
				(b or not x) and
				(not b or x);
			);



	b a x	y
Gruppe 1:
1	0 0 1	1
2	0 1 0	1
Gruppe 2:
6	1 1 0	1
Gruppe 3:
7	1 1 1	1

1		0 0 1
2:6		- 1 0
6:7		1 1 -

		1	2	6	7
1		*
2:6			*	*
6:7				*	*

	y <= (not b and not a and x) or
			(a and not x) or
			(b and a);
	y <= not (
				(b or a or not x) and
				(not a or x) and
				(not b or not a)
			);


	bout <= (not b and a) or
			(not b and not x) or
			(b and x);
	bout <= not (
				(b or not a) and
				(b or x) and
				(not b or not x)
			);
	aout <= (a and x) or
			(not b and x) or
			(b and not x);
	aout <= not(
				(not a or not x) and
				(b or not x) and
				(not b or x);
			);
	y <= (not b and not a and x) or
			(a and not x) or
			(b and a);
	y <= not (
				(b or a or not x) and
				(not a or x) and
				(not b or not a)
			);







library ieee;
use ieee.std_logic_1164.all;

entity meinuebergangsschaltnetz0047 is
port (
	a, b, x: in std_logic;
	bout, aout: out std_logic
);
end;

architecture verhalten of meinuebergangsschaltnetz0047 is
begin
	bout <= (not b and a) or
			(not b and not x) or
			(b and x);
	aout <= (a and x) or
			(not b and x) or
			(b and not x);

end;

library ieee;
use ieee.std_logic_1164.all;

entity meinausgangsschaltnetz0047 is
port
(
	b, a, x: in std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinausgangsschaltnetz0047 is
begin
	y <= (not b and not a and x) or
			(a and not x) or
			(b and a);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomattestbench0047 is
port (
	y: out std_logic;
	bout, aout: out std_logic

);
end;

architecture verhalten of meinautomattestbench0047 is
	component meinausgangsschaltnetz0047
	port (
		b, a, x: in std_logic;
		y: out std_logic
	);
	end component;
	component meinuebergangsschaltnetz0047
	port (
		b, a, x: in std_logic;
		bout, aout: out std_logic
	);
	end component;
	signal b, a, x: std_logic;
begin
	ausgang: meinausgangsschaltnetz0047 PORT MAP (b=>b, a=>a, x=>x, y=>y);
	uebergang: meinuebergangsschaltnetz0047 PORT MAP (b=>b, a=>a, x=>x, bout=>bout, aout=>aout);

	x <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;

	a <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;

	b <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;

end;

Image Screenshot_20231211_073741 

	b a x	b a y
0	0 0 0	1 0 0
1	0 0 1	0 1 1
2	0 1 0	1 0 1
3	0 1 1	1 1 0
4	1 0 0	0 1 0
5	1 0 1	1 0 0
6	1 1 0	0 1 1
7	1 1 1	1 1 1

Image Screenshot_20231211_073741 

library ieee;
use ieee.std_logic_1164.all;

entity meinschaltnetz0047 is
port (
    x3, x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture verhalten of meinschaltnetz0047 is
begin
    y <= (not x3 and not x1 and not x0) or
        (x3 and x2 and not x1) or
        (not x3 and x2 and x1 and x0) or
        (x3 and not x2 and x1 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinetestbench0047 is
port (
    y: out std_logic
);
end;

architecture verhalten of meinetestbench0047 is
    component meinschaltnetz0047
    port (
        x3, x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
    signal x3, x2, x1, x0: std_logic;
begin
    sn: meinschaltnetz0047 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
    x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;

    x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;

    x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;

    x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;

Image Screenshot_20231211_073741 

cat:
	tail -n 80 automat0047.txt > automat0047.vhdl
compile:
	ghdl -a automat0047.vhdl
sim:
	ghdl -r meinautomattestbench0047 --wave=automat0047.ghw
	gtkwave automat0047.ghw