Re: Aufgaben und Übungen,

	b a x	b a y
0	0 0 0	0 0 0
1	0 0 1	1 1 1
2	0 1 0	0 1 1
3	0 1 1	0 0 0
4	1 0 0	0 1 0
5	1 0 1	0 0 1
6	1 1 0	1 1 1
7	1 1 1	0 0 1


	b a x	b
0	0 0 0	0
1	0 0 1	1
2	0 1 0	0
3	0 1 1	0
4	1 0 0	0
5	1 0 1	0
6	1 1 0	1
7	1 1 1	0

	b a x	a
0	0 0 0	0
1	0 0 1	1
2	0 1 0	1
3	0 1 1	0
4	1 0 0	1
5	1 0 1	0
6	1 1 0	1
7	1 1 1	0

	b a x	y
0	0 0 0	0
1	0 0 1	1
2	0 1 0	1
3	0 1 1	0
4	1 0 0	0
5	1 0 1	1
6	1 1 0	1
7	1 1 1	1



	b a x	b
1	0 0 1	1
6	1 1 0	1

	b a x	a
1	0 0 1	1
2	0 1 0	1
4	1 0 0	1
6	1 1 0	1

	b a x	y
1	0 0 1	1
2	0 1 0	1
5	1 0 1	1
6	1 1 0	1
7	1 1 1	1


	b a x	b
Gruppe 1:
1	0 0 1	1
Gruppe 2:
6	1 1 0	1

	b a x	a
Gruppe 1:
1	0 0 1	1
2	0 1 0	1
4	1 0 0	1
Gruppe 2:
6	1 1 0	1

	b a x	y
Gruppe 1:
1	0 0 1	1
2	0 1 0	1
Gruppe 2:
5	1 0 1	1
6	1 1 0	1
Gruppe 3:
7	1 1 1	1



	b a x	b
Gruppe 1:
1	0 0 1	1
Gruppe 2:
6	1 1 0	1

	bout <= (not b and not a and x) or
			(b and a and not x);
	bout <= not (
				(b or a or not x) and
				(not b or not a or x)
			);

	b a x	a
Gruppe 1:
1	0 0 1	1
2	0 1 0	1
4	1 0 0	1
Gruppe 2:
6	1 1 0	1

1		0 0 1
2:6		- 1 0
4:6		1 - 0

		1	2	4	6
1		*
2:6			*		*
4:6				*	*


	aout <= (not b and not a and x) or
			(a and not x) or
			(b and not x);
	aout <= not (
				(b or a or not x) and
				(not a or x) and
				(not b or x)
			);

	b a x	y
Gruppe 1:
1	0 0 1	1
2	0 1 0	1
Gruppe 2:
5	1 0 1	1
6	1 1 0	1
Gruppe 3:
7	1 1 1	1

1:5		- 0 1
2:6		- 1 0
5:7		1 - 1
6:7		1 1 -

		1	2	5	6	7
1:5		*		*
2:6			*		*
5:7				*		*
6:7					*	*

		1	2	5	6	7
1:5		*		*
2:6			*		*
5:7				*		*

		y <= (a xor x) or (b and x)
		y <= (a or not x) and (not a or x) and (not b or not x)


		bout <= (not b and not a and x) or
			(b and a and not x);
		aout <= (not b and not a and x) or
			(a and not x) or
			(b and not x);
		y <= (a xor x) or (b and x);

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0057uebergangsschaltnetz is
port (
	b, a, x: in std_logic;
	bout, aout: out std_logic
);
end;

architecture verhalten of meinautomat0057uebergangsschaltnetz is
begin
		bout <= (not b and not a and x) or
			(b and a and not x);
		aout <= (not b and not a and x) or
			(a and not x) or
			(b and not x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0057ausgangsschaltnetz is
port (
	b, a, x: in std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinautomat0057ausgangsschaltnetz is
begin
		y <= (a xor x) or (b and x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0057testbench is
port (
	bout, aout: out std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinautomat0057testbench is
	component meinautomat0057uebergangsschaltnetz
	port (
		bout, aout: out std_logic;
		b, a, x: in std_logic
	);
	end component;
	component meinautomat0057ausgangsschaltnetz
	port (
		b, a, x: in std_logic;
		y: out std_logic
	);
	end component;
	signal b, a, x: std_logic;
begin
	sn1: meinautomat0057uebergangsschaltnetz PORT MAP (bout=>bout, aout=>aout, b=>b, a=>a, x=>x);
	sn2: meinautomat0057ausgangsschaltnetz PORT MAP (y=>y, b=>b, a=>a, x=>x);

end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0057uebergangsschaltnetz is
port (
	b, a, x: in std_logic;
	bout, aout: out std_logic
);
end;

architecture verhalten of meinautomat0057uebergangsschaltnetz is
begin
		bout <= (not b and not a and x) or
			(b and a and not x);
		aout <= (not b and not a and x) or
			(a and not x) or
			(b and not x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0057ausgangsschaltnetz is
port (
	b, a, x: in std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinautomat0057ausgangsschaltnetz is
begin
		y <= (a xor x) or (b and x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0057testbench is
port (
	bout, aout: out std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinautomat0057testbench is
	component meinautomat0057uebergangsschaltnetz
	port (
		bout, aout: out std_logic;
		b, a, x: in std_logic
	);
	end component;
	component meinautomat0057ausgangsschaltnetz
	port (
		b, a, x: in std_logic;
		y: out std_logic
	);
	end component;
	signal b, a, x: std_logic;
begin
	sn1: meinautomat0057uebergangsschaltnetz PORT MAP (bout=>bout, aout=>aout, b=>b, a=>a, x=>x);
	sn2: meinautomat0057ausgangsschaltnetz PORT MAP (y=>y, b=>b, a=>a, x=>x);
	x <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	a <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	b <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;
end;

	b a x	b a y
0	0 0 0	0 0 0
1	0 0 1	1 1 1
2	0 1 0	0 1 1
3	0 1 1	0 0 0
4	1 0 0	0 1 0
5	1 0 1	0 0 1
6	1 1 0	1 1 1
7	1 1 1	0 0 1