Re: Aufgaben und Übungen,

	b a x	b a y
0	0 0 0	1 0 1
1	0 0 1	0 0 0
2	0 1 0	1 0 1
3	0 1 1	0 1 1
4	1 0 0	0 1 0
5	1 0 1	1 1 1
6	1 1 0	0 0 0
7	1 1 1	0 1 0


	b a x	b
0	0 0 0	1
1	0 0 1	0
2	0 1 0	1
3	0 1 1	0
4	1 0 0	0
5	1 0 1	1
6	1 1 0	0
7	1 1 1	0

	b a x	a
0	0 0 0	0
1	0 0 1	0
2	0 1 0	0
3	0 1 1	1
4	1 0 0	1
5	1 0 1	1
6	1 1 0	0
7	1 1 1	1

	b a x	y
0	0 0 0	1
1	0 0 1	0
2	0 1 0	1
3	0 1 1	1
4	1 0 0	0
5	1 0 1	1
6	1 1 0	0
7	1 1 1	0



	b a x	b
0	0 0 0	1
2	0 1 0	1
5	1 0 1	1

	b a x	a
3	0 1 1	1
4	1 0 0	1
5	1 0 1	1
7	1 1 1	1

	b a x	y
0	0 0 0	1
2	0 1 0	1
3	0 1 1	1
5	1 0 1	1



	b a x	b
Gruppe 0:
0	0 0 0	1
Gruppe 1:
2	0 1 0	1
Gruppe 2:
5	1 0 1	1

	b a x	a
Gruppe 1:
4	1 0 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1
Gruppe 3:
7	1 1 1	1

	b a x	y
Gruppe 0:
0	0 0 0	1
Gruppe 1:
2	0 1 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1


	b a x	b
Gruppe 0:
0	0 0 0	1
Gruppe 1:
2	0 1 0	1
Gruppe 2:
5	1 0 1	1

0;2     0 - 0
5       1 0 1

Minimale Rest"uberdeckung: Obsolet

b <= (not b and not x) or (b and not a and x)

	b a x	a
Gruppe 1:
4	1 0 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1
Gruppe 3:
7	1 1 1	1

4;5     1 0 -
3;7     - 1 1
5;7     1 - 1

Minimale Rest"uberdeckung

        3   4   5   7
4;5         *   *
3;7     *           *
5;7             *   *

        3   4   5   7
4;5         *   *
3;7     *           *

4;5     1 0 -
3;7     - 1 1

a <= (b and not x) or (a and x)



	b a x	y
Gruppe 0:
0	0 0 0	1
Gruppe 1:
2	0 1 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1

0;2     0 - 0
2;3     0 1 -
5       1 0 1

Minimale Rest"uberdeckung

        0   2   3   5
0;2     *   *
2;3         *   *
5                   *

0;2     0 - 0
2;3     0 1 -
5       1 0 1

y <= (not b and not x) or (not b and a) or (b and not a and x)

b <= (not b and not x) or (b and not a and x)
a <= (b and not x) or (a and x)
y <= (not b and not x) or (not b and a) or (b and not a and x)

VHDL-Quelltext

entity meinschaltnetz0002 is
port
(
	bin, ain, x: in bit;
	bout, aout, y; out bit
);
end;

architecture behaviour of meinschaltnetz0002 is
begin
	bout <= (not bin and not x) or (bin and not ain and x);
	aout <= (bin and not x) or (ain and x);
	y <= (not bin and not x) or (not bin and ain) or (bin and not ain and x);
end;