20250913

1.) Rechne die Zahl in binaer Darstellung  in eine Dezimale Darstellung um
1000000010101000b 32936d
2.) Rechne die Zahl in dezimal darstellung in eine Binaerdarstellung um
61565 1111000001111101
3.) Addiere die drei Zahlen schriftlich
            32921
+           56924
+           39200
-----------------
           129045
4.) Subtrahiere die letzten drei Zahlen schriftlich von der ersten schriftlich
            12176
-            3930
-             751
-           13953
-----------------
            -6458
5.) Rechne die Zahl ins zweier komplement um, mit 8 Bit - und subtrahiere diese zahl von der ersten und rechne das Ergebnis nach dezimal
-8 -51 = -59
11111000 11001101 = 11000101
6.) Multipliziere die zwei Zahlen schriftlich
48333*52788 = 2551402404
7.) Dividiere die zwei Zahlen schriftlich
30089/46615 = 0
8.) Errechne x Logarithmisch mit dem Taschenrechner
20889^x = 635745053
9.) Errechne mit dem Abakus
98 + 18 + 53 + 14 + 95 + 50 + 49 + 57 + 32 + 10
10.) Errechne mit dem Abakus
7616 + 7229 + 340 + 9728 + 3122 + 9415 + 9363 + 8257 + 4915 + 5607
;; m8 (ATMega8)
;; (C) David Vajda
;; 2025-09-13
;; PORT D Count - Oszi - high frequency

.include "m8def.inc"

ldi r16, HIGH (RAMEND)
out SPH, r16
ldi r16, LOW (RAMEND)
out SPL, r16

ldi r16, 0xff
out DDRD, r16

ldi r16, 0xff
l1:
com r16
out PORTD, r16
com r16
dec r16
rcall delay
rjmp l1

delay:
push r16
push r17
push r18
ldi r18, 0xff
d1:
ldi r17, 0xff
d2:
ldi r16, 0x04
d3:
dec r16
breq d3
dec r17
breq d2
dec r18
breq d1
pop r18
pop r17
pop r16
ret
Image quine20250913-1 Image quine20250913-2

Image quine420250913-1
Image quine420250913-2
Image quine420250913-3
(C) David Vajda
Sat Sep 13 08:27:42 2025
4 Network - TTL - Disjunktive Normalform

 0 0 0 0 0    1
 1 0 0 0 1    0
 2 0 0 1 0    1
 3 0 0 1 1    0
 4 0 1 0 0    1
 5 0 1 0 1    1
 6 0 1 1 0    0
 7 0 1 1 1    0
 8 1 0 0 0    0
 9 1 0 0 1    1
10 1 0 1 0    1
11 1 0 1 1    0
12 1 1 0 0    1
13 1 1 0 1    0
14 1 1 1 0    0
15 1 1 1 1    0


 0 0 0 0 0    1
 2 0 0 1 0    1
 4 0 1 0 0    1
 5 0 1 0 1    1
 9 1 0 0 1    1
10 1 0 1 0    1
12 1 1 0 0    1

Gruppe 0:
 0 0 0 0 0    1
Gruppe 1:
 2 0 0 1 0    1
 4 0 1 0 0    1
Gruppe 2:
 5 0 1 0 1    1
 9 1 0 0 1    1
10 1 0 1 0    1
12 1 1 0 0    1

0:2         0   0   -   0
0:4         0   -   0   0
2:10        -   0   1   0
4:5         0   1   0   -
4:12        -   1   0   0


4:5         0   1   0   -
0:2         0   0   -   0
0:4         0   -   0   0
2:10        -   0   1   0
4:12        -   1   0   0


        0   2   4   5   10  12
4:5             +   +
0:2     +   +
0:4     +       +
2:10        +               +
4:12            +       +


        0   2   4   5   10  12
4:5             +   +
0:4     +       +
2:10        +               +
4:12            +       +


4:5         0   1   0   -
0:4         0   -   0   0
2:10        -   0   1   0
4:12        -   1   0   0

    y   <=  (not x3 and x2 and not x1) or
            (not x3 and not x1 and not x0) or
            (not x2 and x1 and not x0) or
            (x2 and not x1 and not x0);


-- (C) David Vajda
-- Sat Sep 13 08:27:42 2025
-- 4 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine20250913 is
port (
        x3, x2, x1, x0: in std_logic;
        y: out std_logic
);
end;

architecture behaviour of quine20250913 is
begin
    y   <=  (not x3 and x2 and not x1) or
            (not x3 and not x1 and not x0) or
            (not x2 and x1 and not x0) or
            (x2 and not x1 and not x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250913testbench is
port (
        y: out std_logic
);
end;

architecture behaviour of quine20250913testbench is
        component quine20250913
        port (
                x3, x2, x1, x0: in std_logic;
                y: out std_logic
        );
        end component;
        signal x3, x2, x1, x0: std_logic;
begin
        q: quine20250913 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
-- (C) David Vajda
-- Sat Sep 13 08:27:42 2025
-- 4 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine20250913 is
port (
        x3, x2, x1, x0: in std_logic;
        y: out std_logic
);
end;

architecture behaviour of quine20250913 is
begin
    y   <=  (not x3 and x2 and not x1) or
            (not x3 and not x1 and not x0) or
            (not x2 and x1 and not x0) or
            (x2 and not x1 and not x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250913testbench is
port (
        y: out std_logic
);
end;

architecture behaviour of quine20250913testbench is
        component quine20250913
        port (
                x3, x2, x1, x0: in std_logic;
                y: out std_logic
        );
        end component;
        signal x3, x2, x1, x0: std_logic;
begin
        q: quine20250913 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);


        x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;

        x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;

        x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;

        x3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;
Image quine4net20250913-1


                                GAL16V8

                          -------\___/-------
                      CLK |  1           20 | VCC
                          |                 |
                       X3 |  2           19 | NC
                          |                 |
                       X2 |  3           18 | NC
                          |                 |
                       X1 |  4           17 | NC
                          |                 |
                       X0 |  5           16 | NC
                          |                 |
                       NC |  6           15 | NC
                          |                 |
                       NC |  7           14 | NC
                          |                 |
                       NC |  8           13 | NC
                          |                 |
                       NC |  9           12 | Y
                          |                 |
                      GND | 10           11 | /OE
                          -------------------


Pin 19 = NC           XOR = 0   AC1 = 0
  0  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
  1  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
  2  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
  3  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
  4  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
  5  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
  6  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
  7  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Pin 18 = NC           XOR = 0   AC1 = 0
  8  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
  9  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 10  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 11  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 12  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 13  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 14  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 15  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Pin 17 = NC           XOR = 0   AC1 = 0
 16  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 17  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 18  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 19  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 20  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 21  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 22  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 23  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Pin 16 = NC           XOR = 0   AC1 = 0
 24  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 25  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 26  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 27  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 28  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 29  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 30  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 31  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Pin 15 = NC           XOR = 0   AC1 = 0
 32  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 33  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 34  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 35  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 36  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 37  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 38  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 39  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Pin 14 = NC           XOR = 0   AC1 = 0
 40  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 41  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 42  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 43  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 44  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 45  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 46  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 47  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Pin 13 = NC           XOR = 0   AC1 = 0
 48  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 49  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 50  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 51  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 52  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 53  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 54  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 55  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Pin 12 = Y            XOR = 1   AC1 = 0
 56  -x-- x--- -x-- ---- ---- ---- ---- ----
 57  -x-- ---- -x-- -x-- ---- ---- ---- ----
 58  ---- -x-- -x-- -x-- ---- ---- ---- ----
 59  ---- x--- -x-- -x-- ---- ---- ---- ----
 60  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 61  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 62  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 63  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
GAL16V8
DNFQUINE4NETQUINE20250913DAVIDVAJDA

CLK     X3   X2   X1   X0    NC    NC    NC    NC       GND
/OE      Y   NC   NC   NC    NC    NC    NC    NC       VCC

Y   =   !X3 & X2 & !X1 #
        !X3 & !X1 & !X0 #
        !X2 & !X1 & !X0 #
        X2 & !X1 & !X0;

DESCRIPTION
A QUINE MC CLUSKEY 4 NETWORK, DNF, 20250913

Used Program:   GALasm 2.1
GAL-Assembler:  GALasm 2.1
Device:         GAL16V8

*F0
*G0
*QF2194
*L1792 10110111101111111111111111111111
*L1824 10111111101110111111111111111111
*L1856 11111011101110111111111111111111
*L1888 11110111101110111111111111111111
*L2048 00000001
*L2056 0100010001001110010001100101000101010101010010010100111001000101
*L2120 00000000
*L2128 1111111111111111111111111111111111111111111111111111111111111111
*L2192 1
*L2193 0
*C1b8d
*
5cc5


 Pin # | Name     | Pin Type
-----------------------------
   1   | CLK      | Input
   2   | X3       | Input
   3   | X2       | Input
   4   | X1       | Input
   5   | X0       | Input
   6   | NC       | Input
   7   | NC       | Input
   8   | NC       | Input
   9   | NC       | Input
  10   | GND      | GND
  11   | /OE      | Input
  12   | Y        | Output
  13   | NC       | NC
  14   | NC       | NC
  15   | NC       | NC
  16   | NC       | NC
  17   | NC       | NC
  18   | NC       | NC
  19   | NC       | NC
  20   | VCC      | VCC
Image quine4net20250913x-1 Image Screenshot_20250913_090642 Image Screenshot_20250913_090713 Image Screenshot_20250913_105110 Image Screenshot_20250913_105843 Image Screenshot_20250913_105856 Image Screenshot_20250913_111009 Image Screenshot_20250913_171236
#!/bin/bash

# (C) David Vajda
# 2025-09-13
# wahrscheinlichkeitsrechnungsuebung

i=0
while [ $i -lt 128 ]
do
    s=$(echo "obase=2; ibase=10; $(($RANDOM%16))" | bc)
    echo "scale=5; $s" | bc
    i=$(($i+1))
done