quine20250329.txt

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(C) David Vajda
Sat Mar 29 17:28:46 2025
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		0
 2	0	1	0		1
 3	0	1	1		0
 4	1	0	0		1
 5	1	0	1		1
 6	1	1	0		0
 7	1	1	1		0


	x2	x1	x0		y
 2	0	1	0		1
 4	1	0	0		1
 5	1	0	1		1


	x2	x1	x0		y
Gruppe 1:
 2	0	1	0		1
 4	1	0	0		1
Gruppe 2:
 5	1	0	1		1

2			0	1	0
4:5			1	0	-

	y	<=	(not x2 and x1 and not x0) or
			(x2 and not x1);

library ieee;
use ieee.std_logic_1164.all;

entity quine20250329 is
port (
	x2, x1, x0: in std_logic
	y: out std_logic
);
end;

architecture behaviour of quine20250329 is
begin
	y	<=	(not x2 and x1 and not x0) or
			(x2 and not x1);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20250329testbench is
port (
	y: out std_logics
);
end;

architecture behaviour of quine20250329testbench is
	component quine20250329
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20250329 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);