2024-12-13, VHDL/TTL - Quine Mc Cluskey - 3 Eingabevariablen

Veränderter Übungscode

#include <stdio.h>
#include <stdlib.h>
#include <time.h>


int main (void) {
    int x0, x1, x2;
    time_t t;
    int i;
    struct tm tm = *localtime(&(time_t){time(NULL)});


    srand((unsigned) time(&t));

    printf ("(C) David Vajda\n");
    printf ("%s", asctime(&tm));
    printf ("3 Network - TTL - Disjunktive Normalform\n\n");

    printf ("\tx2\tx1\tx0\t\ty\n");
        for (x2 = 0;  x2 <= 1;  x2++) {
            for (x1 = 0;  x1 <= 1;  x1++) {
                for (x0 = 0;  x0 <= 1;  x0++, i++) {
                    printf( "%2i\t%i\t%i\t%i\t\t%d\n", i, x2, x1, x0, rand () %2);
                }
            }
        }

}

Schlechter Übungscode

(C) David Vajda
Fri Dec 13 12:41:41 2024
3 Network - TTL - Disjunktive Normalform

x2	x1	x0	y
 0 0 0 0    0
 1 0 0 1    0
 2 0 1 0    0
 3 0 1 1    1
 4 1 0 0    1
 5 1 0 1    0
 6 1 1 0    1
 7 1 1 1    1

Nächster

(C) David Vajda
Fri Dec 13 12:42:51 2024
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0	y
 0	0 0 0    1
 1	0 0 1    0
 2	0 1 0    1
 3	0 1 1    1
 4	1 0 0    0
 5	1 0 1    0
 6	1 1 0    0
 7	1 1 1    1

Nächster

(C) David Vajda
Fri Dec 13 12:43:55 2024
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		1
 2	0	1	0		0
 3	0	1	1		0
 4	1	0	0		0
 5	1	0	1		1
 6	1	1	0		0
 7	1	1	1		0

Nächster/Gut

(C) David Vajda
Fri Dec 13 12:44:46 2024
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		0
 2	0	1	0		1
 3	0	1	1		0
 4	1	0	0		1
 5	1	0	1		1
 6	1	1	0		0
 7	1	1	1		1


	x2	x1	x0		y
 2	0	1	0		1
 4	1	0	0		1
 5	1	0	1		1
 7	1	1	1		1


 	x2	x1	x0		y
Gruppe 1:
 2	0	1	0		1
 4	1	0	0		1
Gruppe 2:
 5	1	0	1		1
Gruppe 3:
 7	1	1	1		1

2 		0	1	0
4:5		1	0	-
5:7		1	-	1

		2	4	5	7
2 		+
4:5			+	+
5:7				+	+


2 		0	1	0
4:5		1	0	-
5:7		1	-	1

y	<=	(not x2 and x1 and not x0) or
		(x2 and not x1) or
		(x2 and x0);

y	<=	not (
			(x2 or not x1 or x0) and
			(not x2 or x1) and
			(not x2 or not x0)
		);

library ieee;
use ieee.std_logic_1164.all;

entity quine3_20241213 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine3_20241213 is
begin
y	<=	not (
			(x2 or not x1 or x0) and
			(not x2 or x1) and
			(not x2 or not x0)
		);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine3_20241213testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine3_20241213testbench is
	component quine3_20241213
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine3_20241213 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);

VHDL-Code

-- (C) David Vajda
-- Fri Dec 13 12:44:46 2024
-- 3 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine3_20241213 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine3_20241213 is
begin
	y	<=	(not x2 and x1 and not x0) or
			(x2 and not x1) or
			(x2 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine3_20241213testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine3_20241213testbench is
	component quine3_20241213
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine3_20241213 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);
	x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;
end;

Im ersteren waren die Variablen verdreht