2024-12-14, VHDL/TTL - Quine Mc Cluskey - DNF/KNF

(C) David Vajda
Sat Dec 14 14:41:44 2024
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		0
 1	0	0	1		0
 2	0	1	0		1
 3	0	1	1		1
 4	1	0	0		1
 5	1	0	1		1
 6	1	1	0		1
 7	1	1	1		0


 	x2	x1	x0		y
 2	0	1	0		1
 3	0	1	1		1
 4	1	0	0		1
 5	1	0	1		1
 6	1	1	0		1


  	x2	x1	x0		y
Gruppe 1:
 2	0	1	0		1
 4	1	0	0		1
Gruppe 2:
 3	0	1	1		1
 6	1	1	0		1
 5	1	0	1		1


2:3         0   1   -
2:6         -   1   0
4:6         1   -   0
4:5         1   0   -


2:3         0   1   -
4:5         1   0   -
4:6         1   -   0
2:6         -   1   0

        2   3   4   5   6
2:3     +   +
4:5             +   +
4:6             +       +
2:6     +               +



        2   3   4   5   6
2:3     +   +               p
4:5             +   +       p
4:6             +       +
2:6     +               +


        2   3   4   5   6
2:3     +   +               p
4:5             +   +       p
4:6             +       +

2:3         0   1   -
4:5         1   0   -
4:6         1   -   0

    y   <=  (not x2 and x1) or
            (x2 and not x1) or
            (x2 and not x0);

    y   <=  not (
                (x2 or not x1) and
                (not x2 or x1) and
                (not x2 or x0)
            );

library ieee;
use ieee.std_logic_1164.all;

entity quine3_20241214 is
port (
    x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture behaviour of quine3_20241214 is
begin
    y   <=  (not x2 and x1) or
            (x2 and not x1) or
            (x2 and not x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine3_20241214testbench is
port (
    y: out std_logic
);
end;

architecture behaviour of quine3_20241214testbench is
    component quine3_20241214
    port (
        x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
    signal x2, x1, x0: std_logic;
begin
    q: quine3_20241214 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);

VHDL-Code

-- (C) David Vajda
-- Sat Dec 14 14:41:44 2024
-- 3 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine3_20241214 is
port (
    x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture behaviour of quine3_20241214 is
begin
    y   <=  (not x2 and x1) or
            (x2 and not x1) or
            (x2 and not x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine3_20241214testbench is
port (
    y: out std_logic
);
end;

architecture behaviour of quine3_20241214testbench is
    component quine3_20241214
    port (
        x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
    signal x2, x1, x0: std_logic;
begin
    q: quine3_20241214 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);
    x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;

    x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

    x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;
end;