2024-12-20

(C) David Vajda
Fri Dec 20 15:29:58 2024
3 Network - TTL - Disjunktive Normalform

	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		1
 2	0	1	0		0
 3	0	1	1		0
 4	1	0	0		1
 5	1	0	1		0
 6	1	1	0		0
 7	1	1	1		1


 	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		1
 2	0	1	0		0
 3	0	1	1		0
 4	1	0	0		1
 5	1	0	1		0
 6	1	1	0		0
 7	1	1	1		1


 	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		1
 4	1	0	0		1
 7	1	1	1		1


 	x2	x1	x0		y
 0	0	0	0		1
 1	0	0	1		1
 4	1	0	0		1

0:1		0	0	-
0:4		-	0	0

 7	1	1	1		1

7		1	1	1


		x2	x1	x0		y
0:1		0	0	-		1
0:4		-	0	0		1
7		1	1	1		1

			0	1	4	7
0:1			+	+
0:4			+		+
7						+

		x2	x1	x0		y
0:1		0	0	-		1
0:4		-	0	0		1
7		1	1	1		1


	y	<=	(not x2 and not x1) or
			(not x1 and not x0) or
			(x2 and x1 and x0);

	y	<=	not (
				(x2 or x1) and
				(x1 or x0) and
				(not x2 or not x1 or not x0);
			);

library ieee;
use ieee.std_logic_1164.all;

entity quine20241220_3x_ttl of
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20241220_3x_ttl of
begin
	y	<=	(not x2 and not x1) or
			(not x1 and not x0) or
			(x2 and x1 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20241220_3x_ttl_testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20241220_3x_ttl_testbench is
	component quine20241220_3x_ttl
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20241220_3x_ttl PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);

VHDL-Code:

library ieee;
use ieee.std_logic_1164.all;

entity quine20241220_3x_ttl is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20241220_3x_ttl is
begin
	y	<=	(not x2 and not x1) or
			(not x1 and not x0) or
			(x2 and x1 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20241220_3x_ttl_testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20241220_3x_ttl_testbench is
	component quine20241220_3x_ttl
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20241220_3x_ttl PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);
	x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;
end;