Nächste Seite: 2024-12-28, Zustandsminimierung Aufwärts: phptest20241227.php Vorherige Seite: phptest20241227.php
(C) David Vajda
Fri Dec 27 17:50:49 2024
3 Network - TTL - Disjunktive Normalform
x2 x1 x0 y
0 0 0 0 1
1 0 0 1 1
2 0 1 0 1
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1
x2 x1 x0 y
0 0 0 0 1
1 0 0 1 1
2 0 1 0 1
3 0 1 1 1
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1
x2 x1 x0 y
Gruppe 0:
0 0 0 0 1
Gruppe 1:
1 0 0 1 1
2 0 1 0 1
Gruppe 2:
3 0 1 1 1
5 1 0 1 1
6 1 1 0 1
Gruppe 3:
7 1 1 1 1
0:1 0 0 -
0:2 0 - 0
1:3 0 - 1
1:5 - 0 1
2:3 0 1 -
2:6 - 1 0
3:7 - 1 1
5:7 1 - 1
6:7 1 1 -
0:1 0 0 -
2:3 0 1 -
6:7 1 1 -
0:2 0 - 0
1:3 0 - 1
5:7 1 - 1
1:5 - 0 1
2:6 - 1 0
3:7 - 1 1
0:1 0 0 -
2:3 0 1 -
6:7 1 1 -
0:1:2:3 0 - -
2:3:6:7 - 1 -
0:2 0 - 0
1:3 0 - 1
5:7 1 - 1
0:2:1:3 0 - -
1:3:5:7 - - 1
1:5 - 0 1
2:6 - 1 0
3:7 - 1 1
1:5:2:6 - - 1
2:6:3:7 - 1 -
0:1:2:3 0 - -
2:3:6:7 - 1 -
0:2:1:3 0 - -
1:3:5:7 - - 1
1:5:2:6 - - 1
2:6:3:7 - 1 -
0:1:2:3 0 - -
1:5:2:6 - - 1
2:6:3:7 - 1 -
y <= (not x2) or x0 or x1
library ieee;
use ieee.std_logic_1164.all;
entity quine3_20241227b is
port (
x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine3_20241227b is
begin
y <= (not x2) or x0 or x1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine3_20241227b_testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine3_20241227b_testbench is
component quine3_20241227b
port (
x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x2, x1, x0: std_logic;
begin
q: quine3_20241227b PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);
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-- (C) David Vajda
-- Fri Dec 27 17:50:49 2024
-- 3 Network - TTL - Disjunktive Normalform
library ieee;
use ieee.std_logic_1164.all;
entity quine3_20241227b is
port (
x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine3_20241227b is
begin
y <= (not x2) or x0 or x1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine3_20241227b_testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine3_20241227b_testbench is
component quine3_20241227b
port (
x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x2, x1, x0: std_logic;
begin
q: quine3_20241227b PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);
x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;
x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;
x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;
end;
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