quine20241229_3x.vhdl

-- (C) David Vajda
-- Sun Dec 29 18:45:19 2024
-- 3 Network - TTL - Disjunktive Normalform

library ieee;
use ieee.std_logic_1164.all;

entity quine20241229x3 is
port (
	x2, x1, x0: in std_logic;
	y: out std_logic
);
end;

architecture behaviour of quine20241229x3 is
begin
	y	<=	(not x2 and x0) or
			(x2 and not x0) or
			(x2 and x1);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20241229x3testbench is
port (
	y: out std_logic
);
end;

architecture behaviour of quine20241229x3testbench is
	component quine20241229x3
	port (
		x2, x1, x0: in std_logic;
		y: out std_logic
	);
	end component;
	signal x2, x1, x0: std_logic;
begin
	q: quine20241229x3 PORT MAP (x2=>x2, x1=>x1, x0=>x0, y=>y);

    x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;

    x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

    x2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;
end;